适用于宽带宽输入的TIADC误差校准算法设计

发布时间：2018-03-27 18:19

本文选题：时间交织模数转换器　切入点：迭代算法　出处：《合肥工业大学》2017年硕士论文

【摘要】：随着半导体制造工艺的进步,数字芯片上单片集成度更高,但对于模拟芯片模数转换器(Analog-to-Digital Converter, ADC)的性能提升并不大,设计出高速高精度的模数转换器显得比较困难,而传统的模数转换器已经不能满足人们的需求。时间交织模数转换器(Time-interleaved Aanlog-to-Digital Converter, TIADC)通过多个ADC并行采样实现高速度,成为设计高速度模数转换器的一种主流架构。时间交织模数转换器通过多个通道并行采样实现高速度,但由于工艺制造过程中存在工艺失配,严重影响了系统的性能。本文主要对通道间存在的三种误差进行分析,针对失调误差,本文提出了一种基于自适应迭代的校准算法,该算法通过LMS迭代来估计通道间的失调误差,通过待校准通道输出与参考通道输出做差,实现误差的补偿;针对增益和采样时间误差,本文提出一种基于信号调制的校准算法,该算法利用信号调制基本原理使信号主频点和杂散频点位置互换并构建一个系数使调制后主频点能量幅值与调制前杂散频点能量幅值相等,最后消除由增益和采样时间误差引入的杂散,通过改进算法中的微分器,实现算法对宽带宽输入信号的校准,即算法不受输入信号频率的限制。为了验证算法功能,本文搭建了 4通道12bits 200MHz的时间交织模数转换器模型,在模型中加入三种误差,当输入信号的归一化频率(fin/fs)分别为0.0197、0.3227和0.8019时,经过校准算法后,输出数据的有效位数分别能达到11.65bits、11.69bits和11.61bits,验证了算法不同输入频段内信号的有效性。接着利用verilog语言对算法进行了 RTL代码的设计,并在Modelsim中进行了代码的功能验证,最后将算法放到FPGA开发板上做了硬件验证,同时对算法进行了 DC综合,形式验证、功耗分析和自动布局布线等ASIC流程设计。
[Abstract]:With the progress of semiconductor manufacturing technology, the integration of single chip on digital chip is higher, but the performance of Analog-to-Digital converter (ADCC) is not much improved, so it is difficult to design high speed and high precision ADC. But the traditional analog-to-digital converter can not meet the needs of the people. Time-interleaved Aanlog-to-Digital converter (TIADC) achieves high speed through multiple ADC parallel sampling. Time interleaved ADC achieves high speed through parallel sampling of multiple channels, but due to process mismatch in the process of manufacturing, time interleaved analog-to-digital converter (ADC) has become a mainstream architecture in the design of high speed analog-to-digital converters. In this paper, three kinds of errors between channels are analyzed, and a calibration algorithm based on adaptive iteration is proposed for the misalignment error. The LMS iteration is used to estimate the misalignment error between the channels, and the error compensation is realized by the error between the output of the channel to be calibrated and the output of the reference channel, and a calibration algorithm based on signal modulation is proposed for the error of gain and sampling time. The algorithm uses the basic principle of signal modulation to swap the position between the main frequency point and the stray frequency point, and constructs a coefficient so that the energy amplitude of the main frequency point after modulation is equal to the energy amplitude of the stray frequency point before modulation. Finally, the spurious signal introduced by gain and sampling time error is eliminated. By improving the differentiator in the algorithm, the wide-band input signal is calibrated, that is, the algorithm is not limited by the frequency of the input signal. In this paper, a time-interleaved analog-to-digital converter model of 4-channel 12bits 200MHz is built. Three kinds of errors are added to the model. When the normalized frequency of input signal is 0.0197 / 0.3227 and 0.8019, respectively, after the calibration algorithm, The effective digits of the output data can reach 11.65 bits11.69 bits and 11.61 bitsrespectively, which verify the validity of the algorithm in different input frequency bands. Then, the RTL code is designed by using verilog language, and the function of the code is verified in Modelsim. Finally, the algorithm is applied to the FPGA development board for hardware verification. At the same time, DC synthesis, formal verification, power analysis and automatic layout and routing are used to design the algorithm.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

【参考文献】