SDIO UVM验证IP技术的研究

发布时间：2018-03-28 08:30

本文选题：SDIO　切入点：UVM　出处：《合肥工业大学》2017年硕士论文

【摘要】：随着集成电路的高速发展,芯片复杂度的提升,验证在芯片设计中扮演越来越重要的角色。为了加速产品上市时间,需要提高验证的速度和效率,因此对验证的技术和方法提出了更高的要求。UVM验证方法学提供了层次清晰的业界统一的验证标准,具有很多传统验证方法达不到的优点,尤其其可复用性可加速验证平台的构建。SoC设计需要复用大量的IP核,验证IP可用于SoC的系统级验证,减少验证工程师的工作量,加快验证流程。SDIO接口广泛应用于消费类电子,为移动设备提供高速、低功耗的数据存储和应用功能。在研究UVM技术和分析SDIO接口标准协议的基础上,设计了符合标准SDIO协议的总线功能模型,并采用UVM验证方法学设计了 SDIO验证IP中的各个组件及验证平台,在其中构建了用于统计和收集功能覆盖率的覆盖率模型。最后,在覆盖率驱动下,设计了随机测试、基础测试和错误测试三种测试用例在验证平台中对所设计的SDIO验证IP进行仿真自测试,实现了 100%的功能覆盖率,测试结果表明所设计的验证IP功能正确,可用于验证带有SDIO接口的SoC芯片。
[Abstract]:With the rapid development of integrated circuits and the increase of chip complexity, verification plays a more and more important role in chip design. In order to accelerate the time to market, it is necessary to improve the speed and efficiency of verification. Therefore, higher requirements for verification techniques and methods are put forward. UVM verification methodology provides a clear level of uniform verification standards in the industry, and has many advantages that traditional verification methods cannot achieve. In particular, its reusability can accelerate the construction of verification platform. SoC design needs to reuse a large number of IP cores, verify that IP can be used for system-level verification of SoC, reduce the workload of verification engineers, and speed up the verification process. SDIO interface is widely used in consumer electronics. This paper provides high speed and low power data storage and application for mobile devices. Based on the research of UVM technology and the analysis of SDIO interface standard protocol, a bus function model conforming to the standard SDIO protocol is designed. The components and verification platform of SDIO verification IP are designed by using UVM verification methodology, and the coverage model for statistics and collection function coverage is constructed. Finally, a random test is designed under the driving of coverage. Three kinds of test cases, basic test and error test, simulate and self-test the designed SDIO verification IP in the verification platform, and achieve 100% function coverage. The test results show that the designed verification IP function is correct. Can be used to verify the SoC chip with SDIO interface.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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