具有结型场板的高压LDMOS研究

发布时间：2018-03-28 10:52

本文选题：结型场板　切入点：LDMOS　出处：《电子科技大学》2015年硕士论文

【摘要】：为实现横向功率器件的高耐压和低导通电阻特性,本文提出了一种新型结型场板技术。结型场板技术不仅保持了传统阻性场板在调制器件表面电场方面的优势,而且解决了阻性场板泄漏电流大的问题,对器件静态电学性能的提高具有非常大的作用。本文将结型场板技术应用在LDMOS上,提出了两种新的LDMOS器件。1.一种具有结型场板的REBULF(REduced BULk Field)LDMOS。本文将新型结型场板技术和REBULF技术应用于具有薄外延导电层的高压LDMOS上,提出了JFP-REBULF(Junction Field Plate-Partial N-buried layer)LDMOS结构。结型场板不仅可以调节功率器件的表面电场,还能与漂移区形成MIS结构,辅助耗尽漂移区,增加漂移区掺杂浓度。REBULF技术在衬底内引入了一个纵向的PN结,可扩展衬底纵向耗尽深度,提高器件的纵向耐压。在两种技术的共同作用下,JFPREBULF LDMOS在耐压达到740V的同时,比导通电阻可以低至67.3 mΩ·cm2。相对于传统同尺寸的具有一阶金属场板的LDMOS来说,耐压提高了67.4%,比导通电阻降低了45.7%。本文还根据与我们合作的生产线的工艺条件设计了JFPREBULF LDMOS的工艺流程,并制作了版图。2.一种具有结型场板的LDMOS。考虑到有些应用情况下可以使用电阻率高的硅衬底,纵向耐压不再是薄外延层功率器件的“短板”,本文提出了JFP LDMOS。结型场板在提高器件的耐压的同时还大大地降低了器件的导通电阻。器件的纵向耐压则基本上都由具有低掺杂浓度的衬底承担。与JFP-REBULF LDMOS相比,JFP LDMOS无需制作部分N埋层结构,简化了制造工艺并降低了成本。经过仿真优化设计器件参数获得JFP LDMOS的耐压为679V,比导通电阻为62.4mΩ?cm2,相对于传统的具有一阶金属场板的LDMOS,耐压提高了26.7%,比导通电阻降低了66.4%。最后,本文给出了这种器件的工艺步骤。
[Abstract]:In order to realize the characteristics of high voltage and low on-resistance of transverse power devices, a new type of junction field plate technology is proposed in this paper, which not only maintains the advantage of the traditional resistive field plate in the surface electric field of modulating devices, but also keeps the advantages of the traditional resistive field plate in the surface electric field of modulating devices. Moreover, the problem of large leakage current of resistive field plate is solved, which plays an important role in improving the static electrical performance of the device. In this paper, the junction field plate technology is applied to LDMOS. Two new LDMOS devices are proposed. 1. A new type of REBULF(REduced BULk FieldMoss with junction field plate is proposed. In this paper, a novel junction field plate technique and REBULF technique are applied to high voltage LDMOS with thin epitaxial conductive layer. The JFP-REBULF(Junction Field Plate-Partial N-buried layer)LDMOS structure is proposed. The junction field plate can not only adjust the surface electric field of the power device, but also form MIS structure with the drift region to assist the depletion drift region. A longitudinal PN junction is introduced into the substrate by increasing the drift region doping concentration. It can extend the longitudinal depletion depth of the substrate and improve the longitudinal voltage resistance of the device. The JFPREBULF LDMOS can withstand a voltage of 740V at the same time under the combined action of the two techniques. The specific on-resistance can be as low as 67.3 m 惟 cm2.Compared with the conventional LDMOS with the same size of the first order metal field plate, The voltage resistance is increased by 67.4%, and the on-resistance is reduced by 45.7%. The process of JFPREBULF LDMOS is also designed according to the technological conditions of the production line that we are cooperating with. A kind of LDMOS with junction field plate is fabricated. Considering that silicon substrate with high resistivity can be used in some applications, The longitudinal voltage resistance is no longer the "short board" of the thin epitaxial layer power device. In this paper, it is proposed that the junction field board not only improves the device's voltage resistance, but also greatly reduces the on-resistance of the device. Compared with JFP-REBULF LDMOS, the substrate with low doping concentration does not need to fabricate part of the N-buried structure. The fabrication process is simplified and the cost is reduced. By optimizing the design parameters of the device, the voltage of JFP LDMOS is 679V and the specific on-resistance is 62.4m 惟? Cm _ 2, compared with the conventional LDMOS with first-order metal field plates, increases the voltage by 26.7 and reduces the on-resistance by 66.4. finally, the process steps of this device are given in this paper.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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