基于增强介质层电场技术的新型SOI高压器件研究

发布时间：2018-03-29 06:24

本文选题：SOI　切入点：击穿电压　出处：《重庆大学》2015年硕士论文

【摘要】：SOI(Silicon On Insulator)高压器件因为其独特的一些优点在近年来得以快速的发展。随着对其的不断研究与应用,新的问题也随之而来—SOI高压器件的纵向耐压受到了一些限制。众多的科学家对这一问题都进行了深入的研究。目前,增强介质层电场是提高SOI高压器件耐压的十分有效途径,主要有三类技术:采用超薄顶层硅、引入低介电系数新介质层以及引入界面电荷,其中引入界面电荷是最为有效的方式。目前国际上在SOI器件中引入界面电荷有两种方式:重离子界面固定电荷和界面自适应反型电荷。本文提出高浓度电离施主增强SOI高压器件介质层电场新技术,能够提高器件耐压,并且获得了硅层电场、介质层电场与耐压解析模型。基于此,设计系列新器件结构,主要包括界面N+硅岛系列SOI高压器件结构,基于SIMOX埋氧衬底的部分埋N+层SOI高压器件,以及基于薄埋氧层及三层顶层硅衬底的SOI高压LDMOS器件结构。①界面N+硅岛系列SOI高压器件结构。该类器件在界面处注入等高、等宽、等距的N+硅岛。器件阻断状态时,相邻两个界面N+硅岛内将积累大量反型空穴,同时部分耗尽的N+岛内也会积累高浓度电离施主正电荷,这些正电荷将大大增强埋氧层电场,从而有效提高器件耐压。该类器件包括:(1)1200V级薄硅层P沟道SOI LDMOS器件,在2μm埋氧层及1.5μm顶层硅上实现1224V的高耐压,而埋氧层电场达600V/μm,远远高于常规约100 V/μm的水平;(2)INI PSOI LDMOS器件;(3)界面电荷岛PSOI N沟道LDMOS器件。②基于SIMOX埋氧衬底的部分埋N+层SOI高压器件(PBN SOI)。推导界面电场解析模型,表明界面所积累的反型空穴以及界面N+层内部分耗尽的高浓度电离施主正电荷,可有效增强埋氧层电场,从而提高器件耐压。在10μm顶层硅及0.375μm埋氧层厚度上,新结构的埋氧层电场以及击穿电压较相同尺寸的常规结构分别提高了186.5%和45.4%;③基于薄埋氧层及三层顶层硅衬底的SOI高压LDMOS器件(Triple-Layer Top Silicon,TLTS)。该结构在SOI介质层上界面的顶层硅内引入一高浓度N+层,器件处于反向阻断状态时,高浓度N+部分耗尽,漏端界面处已耗尽N+层内的高浓度电离施主正电荷增强介质层电场,所产生的附加电场将调制漂移区内的电场,防止器件在漏端界面处提前击穿,从而可在较薄的介质层上获得较高耐压,在0.375μm介质层上获得624V耐压且具有较高FOM优值。
[Abstract]:SOI(Silicon on Insulator high voltage devices have been developing rapidly in recent years because of their unique advantages. Many scientists have studied this problem deeply. At present, enhancing the dielectric layer electric field is a very effective way to improve the voltage resistance of SOI high voltage devices. There are mainly three types of technologies: the introduction of ultra-thin top silicon, the introduction of new dielectric layers with low dielectric coefficients, and the introduction of interfacial charges. At present, there are two ways to introduce interface charge in SOI devices: heavy ion interface fixed charge and interface adaptive inverse charge. High concentration ionization donor is proposed in this paper. New Technologies for Enhancement of dielectric layer Electric Field in SOI High Voltage Devices, The analytical model of silicon layer electric field, dielectric layer electric field and voltage resistance is obtained. Based on this, a series of new device structures are designed, including interface N silicon island series SOI high voltage device structure. A partially buried N layer SOI high voltage device based on SIMOX buried oxygen substrate, and a SOI high voltage LDMOS device structure based on thin buried oxygen layer and three layer top silicon substrate. The interface N silicon island series SOI high voltage device structure is constructed. Isometric N silicon island. When the device is blocked, a large number of inversion holes will be accumulated in the adjacent two interface N silicon islands, while the partially depleted N island will also accumulate high concentration ionization donor positive charges, which will greatly enhance the buried oxygen layer electric field. This kind of devices include 1: 1V 1200V thin silicon layer P channel SOI LDMOS device, which can achieve 1224V high voltage on 2 渭 m buried oxygen layer and 1.5 渭 m top silicon. However, the buried oxygen layer electric field is up to 600V/ 渭 m, which is much higher than that of the conventional #number0# V / 渭 m horizontal PSOI PSOI LDMOS device. The interface charge island PSOI N channel LDMOS device .2 is based on the partially buried N layer SOI high voltage device based on the SIMOX buried oxygen substrate. The analytical model of the interface electric field is derived. It is shown that the negative hole accumulated at the interface and the high concentration ionization donor positive charge partially depleted in the interface N layer can effectively enhance the buried oxygen layer electric field, thus improving the device voltage. On the thickness of 10 渭 m top silicon and 0.375 渭 m buried oxygen layer, the electric field of buried oxygen layer can be effectively enhanced. The buried oxygen layer electric field of the new structure and the conventional structure with the same breakdown voltage are increased by 186.5% and 45.445%, respectively. The SOI high voltage LDMOS devices based on thin buried oxygen layer and three layers of top silicon substrate are triple-Layer Top silicon monolithic. The top of the interface of the structure on the SOI dielectric layer is located at the top of the interface. A high concentration N layer is introduced into the silicon layer. When the device is in the reverse blocking state, the high concentration of N is partially depleted, and the high concentration of ionization donor positive charge in the N layer is depleted at the interface of the leakage. The additional electric field will modulate the electric field in the drift region. In order to prevent the device from breaking down early at the interface of the drain end, the device can obtain higher voltage in the thin dielectric layer and 624V in the 0.375 渭 m dielectric layer with high FOM excellent value.
【学位授予单位】：重庆大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN303

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