用于时钟信号发生的锁相环电路的设计

发布时间：2018-03-29 17:38

本文选题：电荷泵锁相环　切入点：二阶开关低通滤波器　出处：《哈尔滨工业大学》2015年硕士论文

【摘要】：片上系统(So C)上通常集成了多个功能模块,每个模块需要不同频率的时钟,而So C上只提供一个固定的参考晶振来产生所需时钟信号。因此So C上需要设计一款用于时钟信号发生的锁相环(PLL)电路。本文设计的用于时钟信号发生的全集成的电荷泵锁相环电路,输入频率范围为5~50MHz,输出频率范围为250~500MHz。本文首先根据电荷泵锁相环基本结构对其各模块建立相应的数学模型,从而建立电荷泵锁相环系统整体的数学模型,根据设计指标完成模型中所涉及的系统参数的计算。再对电荷泵锁环相进行行为级建模,代入计算所得系统参数完成行为级仿真验证。接着介绍了电荷泵锁相环电路中各模块电路的设计过程,对设计的各模块做了大量的仿真和分析。为了改善锁相环的锁定性能,提出了一种二阶开关低通滤波器的电路结构。在环路中用该结构替换传统的二阶环路滤波器,能起到缩短环路锁定时间的作用。本文同时对衬底噪声引起的锁相环输出抖动峰峰值和锁相环的输出相位噪声进行了仿真。本文采用SMIC 0.18μm工艺实现该锁相环电路,并完成版图设计和后仿。PLL输出中心频率为500MHz,频偏为1MHz处PLL输出相位噪为-97.6901d Bc@1MHz。
[Abstract]:The on-chip system is usually integrated with multiple functional modules, each requiring a different frequency clock, On so C, only a fixed reference crystal oscillator is provided to generate the required clock signal. Therefore, it is necessary to design a PLLL circuit for clock signal generation on so C. The full integration for clock signal generation is designed in this paper. The charge pump PLL circuit, The input frequency range is 5 ~ 50 MHz and the output frequency range is 250 ~ 500 MHz. In this paper, the corresponding mathematical model of each module is established according to the basic structure of the charge pump phase-locked loop (CPPLL), and the whole mathematical model of the charge-pump phase-locked loop (CPPLL) system is established in this paper. According to the design index, the calculation of the system parameters involved in the model is completed, and then the behavior level model of the charge pump phase locking is built. Then the design process of each module circuit in the charge pump phase-locked loop circuit is introduced, and a lot of simulation and analysis are done for each module designed. In order to improve the locking performance of the phase-locked loop, In this paper, a circuit structure of second-order switching low-pass filter is proposed, which is used to replace the traditional second-order loop filter in the loop. This paper simulates the output jitter peak of PLL caused by substrate noise and the output phase noise of PLL. In this paper, SMIC 0.18 渭 m technology is used to realize the PLL circuit. The output center frequency is 500MHz and the output phase noise of PLL is -97.6901d Bc@ 1MHz at 1MHz offset.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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