2.4GHz CMOS全数字锁相环的研究与设计

发布时间：2018-03-29 20:15

本文选题：全数字锁相环　切入点：时间数字转换器　出处：《南京邮电大学》2015年硕士论文

【摘要】：随着深亚微米CMOS工艺的发展,工艺尺寸的缩小使模拟电路的设计变得更加复杂,尽可能采用数字电路代替模拟电路成为发展的趋势。锁相环作为时钟产生电路是射频通信系统中的关键模块,其中全数字锁相环具有良好的集成性、可移植性和可编程性,以及能够实现较好的相位噪声指标等优势,得到了越来越广泛的研究和发展。本文着重于2.4GHz CMOS全数字锁相环的研究与设计,主要工作包括:1)首先分析并推导了全数字锁相环的主要性能指标,接着分析了I型和II型全数字锁相环的原理和结构特点,并分析了环路参数对整个环路特性与稳定性的影响。2)提出一种用于时间数字转换器(Time-to-Digital Converter,TDC)的互补比较器的结构,在传统比较器结构的基础上,叠加一个与之互补的比较器,能够消除输出波形的毛刺,降低输入失调电压,提高比较器的工作速度,进而改善比较器的精度。3)提出一种可重构数字滤波器(Digital Loop Filter,DLF),将DLF的参数KP、KI做成芯片外的控制端口,通过片外手动调节来改变芯片内部的参数,可以改变全数字锁相环的带宽,开环和闭环响应,以及幅度响应等,最终能够方便地在片外调节,使环路达到锁定状态。4)分析和设计了一款高精度数控振荡器(Digitally Controlled Oscillator,DCO),文中采用CMOS交叉耦合LC振荡器,包括粗调、中调和精调三个电容阵列和ΔΣ调制器。其中,粗调单元采用MIM电容,中调和精调单元采用两对反向连接的PMOS对管构成MOS电容,本文DCO的增益为300kHz左右,使用ΔΣ调制器后,DCO的分辨率可以达到5kHz左右。本文基于SMIC 0.18μm CMOS工艺进行设计,采用自顶向下的设计方法实现了一款能够产生2.4GHz频段的全数字锁相环,主要模块包括TDC、DLF、DCO、ΔΣ调制器和分频器等。仿真结果表明:在1.8V电源电压下,TDC的分辨率为16.6ps,锁相环输出频率范围为2.33~2.55GHz,相位噪声低于-120.7d Bc/Hz@1MHz,RMS抖动为8.75ps,峰峰值抖动为54.07ps,芯片的总功耗为32.6mW,参考时钟12MHz,锁定时间小于20μs,芯片面积为1.32mm2,满足预期设计要求。
[Abstract]:With the development of deep submicron CMOS process, the design of analog circuit becomes more complicated with the reduction of process size. Using digital circuit instead of analog circuit as far as possible becomes the trend of development. Phase-locked loop as a clock generation circuit is the key module in RF communication system, in which all digital phase-locked loop has good integration, portability and programmability. And can achieve better phase noise index and other advantages, has been more and more extensive research and development. This paper focuses on the research and design of 2.4GHz CMOS all-digital phase-locked loop. The main work includes: (1) first, the main performance indexes of all-digital phase-locked loop are analyzed and deduced, and then the principle and structural characteristics of type I and type II all-digital phase-locked loop are analyzed. The influence of loop parameters on the characteristics and stability of the whole loop is analyzed. 2) A complementary comparator for time-to-digital converter (TDC) is proposed. Based on the traditional comparator structure, a complementary comparator is superimposed. It can eliminate the burr of the output waveform, reduce the input offset voltage, improve the working speed of the comparator, and then improve the precision of the comparator. (3) A reconfigurable digital filter is proposed, which makes the parameter KPKI of DLF into an off-chip control port. By manually adjusting the chip's internal parameters, the bandwidth, open-loop and closed-loop response, and amplitude response of the all-digital phase-locked loop can be changed. Finally, it can be easily adjusted out of the chip. This paper analyzes and designs a high precision numerical controlled oscillator (Digital Controlled Oscillator). In this paper, CMOS cross coupled LC oscillator is used, including three capacitive arrays and 螖危 modulator, which include coarse tuning, middle harmonic and fine tuning. The coarse tuning unit uses MIM capacitor, the middle harmonic fine tuning unit uses two pairs of reverse connected PMOS pairs to form the MOS capacitor. The gain of DCO in this paper is about 300kHz. The resolution of 螖危 modulator can reach about 5kHz. Based on SMIC 0.18 渭 m CMOS process, the top-down design method is used to realize an all-digital phase-locked loop which can generate 2.4GHz band. The main modules include DLFCO, 螖危 modulator and frequency divider, etc. The simulation results show that the resolution of TDC is 16.6 psat 1.8 V, the output frequency range of PLL is 2.33 ~ 2.55 GHz, the phase noise is lower than -120.7d BcP / Hz RMS jitter is 8.75 psand the peak jitter is 54.07 ps. the phase noise is less than -120.7d Bc / Hzjunction 1MHzRMS jitter is 8.75ps. the peak jitter is 54.07ps. the phase noise is lower than -120.7d, and the peak jitter is 54.07ps. The total power consumption is 32.6mW, the reference clock is 12MHz, the locking time is less than 20 渭 s, and the chip area is 1.32mm2.It meets the expected design requirements.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN79

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