基于忆阻器的全差分局部无源内插TDC设计

发布时间：2018-03-30 13:14

本文选题：忆阻器　切入点：时间数字转换器　出处：《国防科学技术大学》2015年硕士论文

【摘要】：随着CMOS工艺制程即将走到尽头,亟需各种新材料和新技术来延续和超越摩尔定律。忆阻器作为最新出现的第四种无源器件,被认为是最具发展潜力的替换器件之一。与CMOS工艺的兼容性使它有望首先在与CMOS混合的集成电路中展开大规模应用。与此同时,在进入亚纳米工艺后电源电压已经低至0.9伏以下,传统的在电压域处理信号的部件很难再获得更高和稳定的性能,而基于时间域设计的时间数字转换器(TDC)则为信号处理难题提供了新思路。因此本课题利用忆阻器的阻值记忆效应、纳米级的尺寸和阈值特性,研究一种与CMOS相结合的TDC电路,重点关注结构的实现方式及如何获得高性能的方法。本文的研究工作和创新成果包括以下几个方面:?建立了改进的忆阻器阈值模型,并通过了Hspice仿真验证。?提出了基于忆阻器的可编程延迟单元,通过Hspice仿真验证了该延迟单元具有延时精确可编程的特性,有效地突破了传统CMOS数控延迟单元的控制瓶颈。?采用了基于忆阻器的可编程延迟单元和全差分延迟链的结构,设计了一款基于忆阻器的全差分局部无源内插TDC,并提出了一种新的脉冲序列校准方法,使得延迟分辨率达到亚门级2.25ps,最大差分非线性0.75LSB,最大积分非线性0.51LSB,同时兼具对工艺偏差不敏感的特点。?基于所提出的全差分局部无源内插TDC设计实现了一款工艺偏差传感侦测电路,通过蒙特卡罗分析,表明该TDC能有效完成偏差侦测任务,具有良好的可移植性和实用性。本文的研究工作从器件模型、电路结构和应用等方面系统的体现了以忆阻器和TDC为核心的新器件、新电路研究成功,为纳米集成电路的进一步研究提供了新的思路。
[Abstract]:With the CMOS process coming to an end, new materials and technologies are urgently needed to extend and transcend Moore's law. It is considered one of the most promising alternative devices. Compatibility with the CMOS process promises to be the first to launch large-scale applications in integrated circuits mixed with CMOS. After entering the sub-nanoscale process, the power supply voltage is as low as 0.9 volts, and it is difficult to obtain higher and more stable performance by traditional signal processing components in the voltage domain. The time-digital converter (TDC) based on time domain provides a new idea for the signal processing problem. Therefore, a novel TDC circuit combined with CMOS is studied by using the resistive memory effect of the resistor, the size and threshold characteristics of the nano-scale. Focus on the implementation of the structure and how to achieve high performance. The research work and innovative results include the following aspects:? An improved threshold model of the resistive device is established, and the model is verified by Hspice simulation.? In this paper, a programmable delay unit based on resistor is proposed. The Hspice simulation proves that the delay cell has the characteristic of delay precision and programmable, which effectively breaks through the control bottleneck of traditional CMOS numerical control delay cell.? Using the structure of programmable delay unit and fully differential delay chain based on resistor, a fully differential local passive interpolation TDCbased on resistor is designed, and a new method of pulse sequence calibration is proposed. The delay resolution reaches 2. 25 ps. the maximum difference nonlinearity is 0. 75 LSBs, the maximum integral nonlinearity is 0. 51 LSBs, and the delay resolution is insensitive to process deviation. Based on the fully differential partial passive interpolation TDC, a process bias sensing circuit is designed and implemented. The Monte Carlo analysis shows that the TDC can effectively accomplish the deviation detection task. It has good portability and practicability. The research work of this paper systematically embodies the new device with the core of resistor and TDC in the aspects of device model, circuit structure and application, and the new circuit is studied successfully. It provides a new idea for the further study of nanoscale integrated circuits.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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