13GHz VCO及锁相环设计

发布时间：2018-03-31 04:33

本文选题：整数频率综合器　切入点：电荷泵锁相环　出处：《东南大学》2016年硕士论文

【摘要】：无线收发系统的主要模块包括收发链路以及频率综合器(frequency synthesizer, FS),尤其是频率综合器(频综)是影响无线收发系统的信号质量的重要因素,为其提供本地振荡信号。压控振荡器(voltage controlled oscillator, VCO)和预二分频器在基于锁相环的频综中工作频率最高,性能的好坏是频综能够稳定工作的关键和前提。本文首先详述了频综在通信系统的功能以及指标,在介绍锁相环(phase-locked loop, PLL)式频综的工作原理、噪声模型以及线性化模型的基础上,确定了频综结构,并根据最大相位裕量法以及综合考虑噪声杂散等指标,进行环路参数设计。然后,详述了VCO的种类和性能指标,确定了电感电容压控振荡器(LC voltage controlled oscillator, LC-VCO)的结构和各模块电路级参数,并且详述了预二分频器的类型并确定了结构,进行理论性分析和设计参数,给出了仿真以及测试结果。最后,对频综其他电路(鉴频鉴相器／电荷泵、分频器)行为级建模,并对附加电路(自动增益控制、串行外设接口、时序控制模块)编写Verilog代码并对整个PLL数模混合仿真,给出了仿真结果。本文采用的是TSMC0.13μmCMOS工艺,设计了一个全N型金属-氧化物-半导体(N metal oxide semiconductor, NMOS)的LC-VCO以及基于电流模式逻辑(current mode logic, CML)锁存器的预二分频器,对其设计并且流片测试。同时,本文完成了整数PLL的数模混合仿真。在片测试结果表明,1.2V电源电压下,LC-VCO的输出频率为12.4-15.2GHz,在15.2GHz频率下相位噪声为-119.74dBc/Hz@1MHz,输出功率为0.66dBm,核心电路功耗为11.88mA,核心面积为0.56×0.84 mm2；预二分频器的自激频率为17GHz,频率范围为11-21GHz,电流5.12mA,核心面积约30x25um2；数模混合电路中,串行外设接口(serial peripheral interface, SPI)的工作时间是3.2us,自动频率校准(automatic frequency control, AFC)工作6 us左右,选择好调谐曲线后,锁相环工作14us左右,因此,经过24us,得到期望的频率16GHz,此时调谐电压幅度为0.7325V,波动约0.9mV。
[Abstract]:The main modules of the wireless transceiver system include the transceiver link and frequency synthesizer, especially the frequency synthesizer, especially the frequency synthesizer (FSS), which is an important factor that affects the signal quality of the wireless transceiver system, and provides the local oscillation signal for the wireless transceiver system.Voltage controlled oscillator (VCO) and prescaler have the highest frequency in frequency synthesizer based on phase-locked loop. The performance of VCO is the key and prerequisite for the stability of frequency synthesizer.In this paper, the function and index of frequency synthesizer in communication system are described in detail. Based on the introduction of the working principle, noise model and linearization model of phase-locked loop phase-locked loop (PLL) frequency ensemble, the structure of frequency synthesizer is determined.The loop parameters are designed according to the maximum phase margin method and the noise stray index.Then, the types and performance indexes of VCO are described in detail, the structure of LC voltage controlled oscillator (LC-VCO) and the circuit level parameters of each module are determined, and the type and structure of the predivider are described.The theoretical analysis and design parameters are carried out, and the simulation and test results are given.Finally, the behavior level of other frequency synthesizer circuits (phase discriminator / charge pump, frequency divider) is modeled, and the additional circuits (automatic gain control, serial peripheral interface, timing control module) are programmed Verilog code and the whole PLL digital-analog hybrid simulation is carried out.The simulation results are given.In this paper, the TSMC0.13 渭 mCMOS process is used to design an all-N-type metal-oxide-semiconductor N metal oxide semiconductors (NMOS) LC-VCO and a prescaler based on current-mode logic current mode logic latch.At the same time, the mixed simulation of integer PLL is completed.The results of chip test show that the output frequency of LC-VCO is 12.4-15.2GHz at the voltage of 1.2V, and the phase noise is -119.74dBc / Hz at 15.2GHz frequency, the output power is 0.66dBm, the power consumption of core circuit is 11.88mAand the core area is 0.56 脳 0.84mm2.The self-excitation frequency of the predivider is 17GHz and the frequency range is 17GHz.For 11-21GHz, current 5.12mA, core area about 30x25um2. in digital-analog hybrid circuit,The serial peripheral interface (SPI) has a working time of 3.2 us.After selecting the tuning curve, the phase locked loop (PLL) works about 14us, and the automatic frequency control (AFC) works about 6 us.After 24 uss, the desired frequency is 16 GHz, and the tunable voltage amplitude is 0.7325 V, fluctuating about 0.9 MV.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN752;TN911.8

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