数字频率合成技术在信号源中的应用研究

发布时间：2018-04-03 00:11

本文选题：FPGA　切入点：高速数字电路　出处：《中北大学》2015年硕士论文

【摘要】：随着无线通信与计算技术以及信号处理与分析技术的发展，数字频率合成技术已在雷达、通信、地震勘探、智能仪器、科学实验等各个方面有了广泛的应用。针对传统数字合成系统存在的便捷性差、人机交互不友好、实时性差、智能化程度低等弱点，本文设计了以FPGA为核心的数字信号处理硬件电路，采用VHDL硬件描述语言实现FPGA内逻辑设计，在VC2010平台上用C++语言开发了上位机软件，以上三部分的设计组成了数字频率合成的信号源系统。系统拟采用高速FPGA作为数字信号处理的核心元件，主要实现对系统的时序控制，任务调度，逻辑粘合、波形文件存储控制、读取，数据的并串转换、输出以及与上位机的通信控制。根据FPGA所需要处理的信号设计了高速DA数模转换硬件电路。应用VC2010作为软件平台设计了操控界面，其主要用于实现函数波形的计算、生成及加载。采用硬件描述语言对所需电路模块进行了嵌入式硬件设计。测试结果表明该信号源有良好的交互性，频率准确性和宽范围应用性。在FPGA模块设计中，用VHDL语言编制了相应的时序电路和缓冲FIFO，并充分利用FPGA中丰富的时序资源，如锁相环PLL、触发器，缓冲器FIFO等，完成对系统输入输出时钟的控制。本设计对数字逻辑设计中的部分模块给出了相应的仿真结果和详细的说明以及时序分析。同时，，根据芯片AD9736数模转换器件的时序配置要求，在Xilinx ISEdesign12.3环境下设计了输出控制的状态机。
[Abstract]:With the development of wireless communication and computing technology as well as signal processing and analysis technology, digital frequency synthesis technology has been widely used in radar, communication, seismic exploration, intelligent instruments, scientific experiments and so on.Aiming at the disadvantages of the traditional digital synthesis system, such as poor convenience, unfriendly human-computer interaction, poor real-time and low intelligence, the hardware circuit of digital signal processing based on FPGA is designed in this paper.The hardware description language of VHDL is used to realize the logic design of FPGA, and the software of upper computer is developed in C language on the platform of VC2010. The signal source system of digital frequency synthesis is made up of the design of the above three parts.The system adopts high speed FPGA as the core component of digital signal processing, which mainly realizes the timing control, task scheduling, logic bonding, waveform file storage control, reading, data parallel string conversion, etc.Output and communication control with host computer.A high speed DA digital-analog conversion hardware circuit is designed according to the signal needed by FPGA.The control interface is designed by using VC2010 as the software platform, which is mainly used to calculate, generate and load the function waveform.The embedded hardware is designed with hardware description language.The test results show that the signal source has good interactivity, frequency accuracy and wide application.In the design of FPGA module, the corresponding sequential circuit and buffer FIFO are programmed in VHDL language, and the abundant timing resources in FPGA, such as PLL, trigger, FIFO, etc., are fully utilized to control the system input and output clock.The simulation results, detailed explanation and timing analysis of some modules in digital logic design are given in this design.At the same time, the output control state machine is designed under the Xilinx / ISEdesign12.3 environment according to the timing configuration requirements of the chip AD9736 digital-to-analog converter.
【学位授予单位】：中北大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN74

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