纳米级工艺VLSI芯片低功耗物理设计研究

发布时间：2018-04-10 01:18

本文选题：低功耗物理设计　切入点：多电源电压　出处：《杭州电子科技大学》2015年硕士论文

【摘要】：随着集成电路工艺技术的不断发展,晶体管的特征尺寸不断缩小,芯片单位面积上集成的晶体管数目越来越多。当晶体管的特征尺寸减小到纳米级时,一些超大规模集成电路(VLSI)芯片上集成的晶体管数目己高达上千亿门。同时,由于晶体管的特征尺寸不断缩小,其泄漏电流所引起的静态功耗急剧上升,使得功耗在现阶段的集成电路设计中已受到越来越多的关注。功耗会影响芯片的封装和成本,同时功耗的不断增加还会产生例如电迁移等一系列问题,从而使芯片的可靠性降低。这些因素使得集成电路设计者不得不加大对芯片功耗设计的研究。本文首先介绍了低功耗技术所面临的的挑战、国内外研究现状以及研究意义。接着具体分析了功耗的组成,并从工艺级、电路级、门级和系统级等方面探讨了降低功耗的方法。然后以sblk_dfttr_vdci模块为例,简要地介绍了基于Golden UPF (Unified Power Format)的低功耗物理设计流程,完成了从Netlist到GDS2的全过程设计。再接着本文对模块中所使用的多电源电压和门控电源技术的物理实现,特别是对于多电源电压域的创建、电平转换器的插入和隔离单元的插入等过程进行了详细探讨。最后对完成低功耗物理设计的模块进行了总功耗和功耗完整性的分析。对于总功耗的验证,使用Synopsys公司的PrimetimePX工具,其分析的结果显示完全满足模块对于功耗的要求;对于功耗完整性的分析,主要从电压降和电迁移这两方面来进行；从Apache公司的Redhawk工具分析的结果看,动态电压降、静态电压降和抗电迁移的结果良好,满足模块的设计要求。本文的亮点在于：对于TSMC 28nm工艺的sblk_dfttr_vdci模块,采用新型的基于GoldenUPF的低功耗物理设计流程,完成多电源电压和门控电源等低功耗技术的设计和物理实现,使其模块达到功耗设计的目标。在本文中,对于门控电源和多电源电压低功耗技术的物理实现过程中的难点和重点进行了详细并且深入地探讨,特别是对于多电源电压域的创建、电平转换器的插入、电平转换器的电源线的连接、电源开关单元的插入和隔离单元的插入等提供了详细的实现过程,可以为研究低功耗物理设计的工程师提供一定的参考,并为以后的项目奠定基础。
[Abstract]:With the development of integrated circuit technology, the characteristic size of transistors is shrinking and the number of integrated transistors per unit area is increasing.When the characteristic size of transistors is reduced to nanoscale, the number of transistors integrated on some VLSI chips has reached hundreds of billions.At the same time, the static power consumption caused by the leakage current of transistors increases sharply due to the decreasing characteristic size of transistors, which makes the power consumption more and more concerned in the current integrated circuit design.The power consumption will affect the packaging and cost of the chip, and the increasing power consumption will cause a series of problems, such as electromigration, which will reduce the reliability of the chip.These factors make IC designers have to increase the research on chip power design.This paper first introduces the challenges faced by low-power technology, research status and significance at home and abroad.Then, the composition of power consumption is analyzed in detail, and the methods of reducing power consumption are discussed from the aspects of process level, circuit level, gate level and system level.Then taking the sblk_dfttr_vdci module as an example, this paper briefly introduces the low-power physical design flow based on Golden UPF Unified Power format, and completes the whole process design from Netlist to GDS2.Then the physical realization of multi-power supply voltage and gated power technology used in the module is discussed in detail, especially for the creation of multi-power voltage domain, the insertion of level converter and the insertion of isolation unit.Finally, the overall power consumption and power integrity of the low-power physical design module are analyzed.For the verification of total power consumption, the analysis results of PrimetimePX tool of Synopsys Company show that the power consumption requirements of the module are fully met, and the power integrity analysis is mainly carried out from voltage drop and electromigration.From the analysis of Redhawk tools of Apache Company, it can be seen that the results of dynamic voltage drop, static voltage drop and resistance to electromigration are good, which meet the design requirements of the module.The highlight of this paper lies in: for the sblk_dfttr_vdci module of TSMC 28nm process, a new low-power physical design flow based on GoldenUPF is adopted to complete the design and physical realization of low-power technology such as multi-power supply voltage and gated power supply.Make its module achieve the goal of power design.In this paper, the difficulties and emphases in the physical implementation of gated power supply and multi-power voltage low-power technology are discussed in detail and deeply, especially for the establishment of multi-source voltage domain and the insertion of level converter.The connection of the power line of the level converter, the insertion of the power switch unit and the insertion of the isolation unit provide a detailed implementation process, which can provide a certain reference for the engineers who study the low-power physical design.And lay the foundation for future projects.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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