针对传输线的高速收发器研究

发布时间：2018-04-10 04:22

本文选题：传输线　切入点：信号完整性　出处：《西安电子科技大学》2015年硕士论文

【摘要】：随着集成电路各项技术和工艺的飞速发展,片上高速传输技术将面临更高的要求和更大的挑战。这是因为数据传输速率的提高会导致串扰、损耗和反射等一系列信号完整性问题,又由于线间耦合和对地耦合带来的影响不断加大,长互连线上出现了明显的传输线效应,传统的RC互连已经不能很好地表征信号高速传输时的各项特性。为了解决上述问题,使用传输线模型来代替RC互连模型。同时,高性能的片上收发器可以进一步提高工作频率,降低互连功耗,在降低信号衰减和抑制码间干扰方面也具有明显的作用。因此,针对传输线模型的高速收发器研究就变得十分重要。本文首先介绍了片上高速传输的研究背景和意义,然后从传输线模型出发,研究高速传输时会遇到的信号完整性问题,分析了反射、串扰和损耗等非理想效应的产生原因,给出抑制策略。并针对片上差分传输线,对互连寄生参数进行了提取,得到寄生电阻、电容和电感的表达式。其次,为了解决长距离传输过程中的信道损耗和码间干扰等问题,本文以收发器的预加重技术和时域均衡技术为基础,研究了一种可用于片上高速信号传输的CML收发器,并完成版图的绘制和仿真验证。仿真结果表明,该收发器能够在130nm CMOS混合信号电路工艺下,实现5Gbps的高速信号在10mm长差分传输线上的高性能传输。最后为了验证收发器的实际功能,基于不同的传输线结构,设计出相应的测试实验方案。
[Abstract]:With the rapid development of integrated circuit technology and technology, high-speed transmission technology on-chip will face higher requirements and greater challenges.This is because the increase of data transmission rate will lead to a series of signal integrity problems, such as crosstalk, loss and reflection.Traditional RC interconnection can not well characterize the characteristics of high-speed signal transmission.In order to solve the above problem, the transmission line model is used to replace the RC interconnection model.At the same time, the high performance on-chip transceiver can further improve the working frequency, reduce the power consumption of interconnect, and play a significant role in reducing the signal attenuation and inter-symbol interference (ISI).Therefore, the research of high-speed transceiver for transmission line model becomes very important.This paper first introduces the research background and significance of high speed transmission on a chip, then from the transmission line model, studies the signal integrity problems encountered in high speed transmission, and analyzes the causes of non-ideal effects such as reflection, crosstalk and loss.The inhibition strategy is given.The parasitic parameters of interconnect are extracted for the differential transmission line on chip, and the expressions of parasitic resistance, capacitance and inductance are obtained.Secondly, in order to solve the problems of channel loss and inter-symbol interference during long distance transmission, a CML transceiver which can be used for high speed signal transmission on chip is studied based on transceiver preweighting technique and time domain equalization technique.And complete the layout of the drawing and simulation verification.The simulation results show that the transceiver can realize the high performance transmission of the 5Gbps signal on the 10mm long differential transmission line under the 130nm CMOS mixed signal circuit technology.Finally, in order to verify the actual function of transceiver, the corresponding test scheme is designed based on different transmission line structure.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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