SerDes接收系统中低功耗时钟数据恢复电路的设计

发布时间：2018-04-11 14:39

本文选题：SerDes + 时钟数据恢复　；参考：《东南大学》2016年硕士论文

【摘要】：随着人类信息量的不断增长,高速串行通信正变得越来越重要,一种原本用于光纤通信的SerDes技术以其速度高、容量大、成本低、抗干扰能力强等特点正成为高速串行通信的主流。本论文设计的时钟数据恢复(Clock and Data Recovery, CDR)电路是SerDes接收电路中的一个重要模块,采用TSMC0.18μmCMOS工艺设计,为3.125Gb/s SerDes接收系统提供时钟信号的同时,完成数据的恢复功能。本论文设计的CDR电路基于锁相环(Phase-Locked Loop, PLL)结构,输入3.125Gb/s的不归零(Non Return to Zero, NRZ)数据,输出1.5625GHz的时钟信号和两路1.5625Gb/s的NRZ数据。为了降低系统功耗,电路采用1.2V的低电压供电,利用低功耗的低压差线性稳压器(Low-Dropout Regulator, LDO)完成电压转换的同时,提高CDR系统的电源噪声抑制性能。鉴相器(Phase Detector,PD)采用全CMOS逻辑的半速率线性鉴相器结构,可以降低压控振荡器(Voltage Controlled Oscillator,VCO)的振荡频率,从而降低功耗,VCO采用三级环形伪差分结构。CDR电路利用电荷泵(Charge Pump,CP)完成电压到电流的转变,采用电流转向技术提高CP的工作速度,CP中的单位增益跟随器采用rail-to-rail结构以提高CP的输出电压范围。CDR电路芯片面积为0.321mm×0.534mm,LDO芯片面积为0.3mm×0.375mm。后仿真结果看出,TT工艺角下,负载为50Ω时,CDR电路输出时钟频率为1.5625GHz,恢复出的两路1.5625Gb/s NRZ数据逻辑正确,时钟峰峰值抖动为0.0626UI,两路数据峰峰值抖动分别为0.0497UI和0.0523UI。CDR电路的核心功耗为6.3mW,锁定时间116.9ns。LDO能够为CDR电路提供精准的电源电压,其输出电压温度漂移为3.4ppm,频率在1kHz以内的电源抑制(Power Supply Rejection, PSR)为-62.34dB。
[Abstract]:With the continuous growth of human information, high-speed serial communication is becoming more and more important, an originally used in optical fiber communication SerDes technology with its high speed, large capacity, low cost, strong anti-interference is becoming the mainstream of high-speed serial communication. The design of clock and data recovery (Clock and Data Recovery. CDR) circuit is an important module of SerDes receiving circuit, using the TSMC0.18 mCMOS process design, provides the clock signal at the same time as the 3.125Gb/s SerDes receiver system, complete the data recovery function. The phase-locked loop CDR circuit designed in this paper based on (Phase-Locked, Loop, PLL), not zero input 3.125Gb/s (Non Return to Zero, NRZ) data, NRZ data output clock signal 1.5625GHz and two 1.5625Gb/s. In order to reduce system power consumption, low voltage power supply circuit using 1.2V, using low power low dropout line Regulator (Low-Dropout Regulator, LDO) to complete the voltage conversion at the same time, improve the power supply noise suppression performance of CDR system. The phase detector (Phase Detector, PD) by half rate linear phase CMOS logic phase detector structure, can reduce the voltage controlled oscillator (Voltage Controlled, Oscillator, VCO) of the oscillation frequency, thereby reducing power consumption VCO, the three annular Pseudo differential charge pump circuit by using.CDR (Charge Pump CP) to complete the voltage to current change, the current steering technology to improve the working speed of CP, unit gain in CP follower using rail-to-rail structure to improve the output voltage range of.CDR CP circuit chip area is 0.321mm * 0.534mm. LDO chip area is 0.3mm * see the simulation results of 0.375mm., TT corner, the load is 50 CDR, the output circuit of the clock frequency of 1.5625GHz, the correct two 1.5625Gb/s NRZ data to recover the logic The clock jitter is 0.0626UI, peak peak jitter, two data respectively as the core of power 0.0497UI and 0.0523UI.CDR circuit for 6.3mW, lock time 116.9ns.LDO can provide accurate supply voltage for the CDR circuit, the output voltage of the temperature drift is 3.4PPM, power frequency within 1kHz suppression (Power Supply Rejection, PSR -62.34dB.)

【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN432

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