14位高速高精度CMOS数模转换器研究

发布时间：2018-04-12 17:15

本文选题：电流舵 + 高速DAC　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着无线通信的领域的迅猛发展,数模转换器以及模数转换器做为连接模拟信号与数字信号之间连接的枢纽,其重要性越来越高。由于数字电路处理速度的迅速提升,高性能的数模以及模数转换器的发展就成为了制约整个通讯芯片产业发展的重要因素。同时随着如今工艺尺寸的不断缩小,模拟芯片的设计难度也在不断的提高,这就给高性能DAC的设计者带来了巨大的挑战。电流舵DAC由于其能够支持极高采样率以及对于标准工艺的优秀兼容性,一直以来都是超高速DAC设计者们常用的主要结构。但是电流舵DAC也不可避免的存在着许多不足的地方,开关信号产生的毛刺能量以及电流源阵列内所存在的各种静态以及动态失配会很大程度上限制DAC的线性度。本文针对以上影响进行了优化与改进从而提升了DAC的线性度。本文基于SMIC0.18μm的标准CMOS生产工艺进行设计,设计了一款采样速率最高能够达到3GSPS的14位高速高精度电流舵DAC。此DAC采用了高4位低10位的分段式译码结构对输入信号进行译码,其中高位采用了改进型的分组随机旋转二进制译码结构对输入的数字信号进行译码。采用此译码方式能够有效的在电路的复杂度以及电路动态匹配性能之间寻找平衡点,随后使用四通道数据内插技术对经过译码之后的四路低频采样信号进行内插组合而成一个最高能够达到3GSPS的高频采样信号从而达到提升DAC动态性能的目的,本文所采用的单位电流源使用的共源共栅的结构来提升电流源的的输出阻抗,同时采用了四相开关结构来降低控制信号翻转产生的毛刺对于DAC线性度的影响,提高DAC的整体性能。对整体电路进行了基本功能的仿真以及无杂散动态范围(SFDR)的仿真,仿真结果显示在采样频率达到3GHz的情况下SFDR达到了75dB。在版图的绘制阶段使用了Cadence环境下的Virtuoso图形化版图设计工具对版图进行了设计,严格按照SMIC工艺的要求以及模拟版图设计方法进行仔细的设计,而且在设计的过程中考虑到工艺失配的影响运用了电流源阵列匹配技术对电流源阵列的版图进行优化设计。
[Abstract]:With the rapid development of wireless communication, digital to analog converters and analog-to-digital converters are becoming more and more important for connecting analog and digital signals.With the rapid improvement of the processing speed of digital circuits, the development of high performance digital-to-analog (A / A) and analog-to-digital converters (ADC) has become an important factor restricting the development of the whole communication chip industry.At the same time, with the continuous reduction of process size, the design difficulty of analog chip is also increasing, which brings great challenges to the designers of high-performance DAC.Because of its ability to support extremely high sampling rate and excellent compatibility with standard process, the current steering DAC has always been the main structure commonly used by DAC designers.However, there are many disadvantages in the current steering DAC. The burr energy generated by the switch signal and the various static and dynamic mismatch in the current source array will limit the linearity of the DAC to a great extent.In order to improve the linearity of DAC, the above effects are optimized and improved in this paper.Based on the standard CMOS process of SMIC0.18 渭 m, a 14 bit high speed and high precision current rudder DAC with the highest sampling rate up to 3GSPS is designed in this paper.In this DAC, the input signal is decoded with a segmented decoding structure with high 4 bits and low 10 bits, and the input digital signal is decoded in high position with an improved packet random rotation binary decoding structure.This decoding method can effectively find the balance point between the complexity of the circuit and the dynamic matching performance of the circuit.Then the four-channel data interpolation technique is used to interpolate the four channels of low-frequency sampling signals after decoding to form a high-frequency sampling signal which can achieve the maximum 3GSPS, thus achieving the purpose of improving the dynamic performance of DAC.In this paper, the output impedance of the current source is raised by using the common gate structure of the unit current source and the four-phase switching structure is used to reduce the effect of burrs produced by the control signal flipping on the linearity of the DAC.Improve the overall performance of DAC.The basic functions of the whole circuit and the simulation of SFDR without spurious dynamic range are simulated. The simulation results show that the SFDR reaches 75 dB when the sampling frequency reaches 3GHz.In the drawing stage of layout, the Virtuoso graphic layout design tool under Cadence environment is used to design the layout. The layout is carefully designed according to the requirements of SMIC process and the method of analog layout design.Considering the influence of process mismatch, the current source array matching technique is used to optimize the layout of current source array.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

【相似文献】