一种Sigma-Delta MASH结构四阶调制器的设计

发布时间：2018-04-13 00:09

本文选题：Sigma-Delta调制器 + MASH结构　；参考：《哈尔滨工业大学》2017年硕士论文

【摘要】：数字硅陀螺接口电路无论是在军事领域还是在日常生活中都占有很重要的地位,而自然界中连续的物理量采集变成更易操作的离散值就离不开模数转化器(ADC)这个媒介。Sigma-Delta(ΣΔ)调制器又是ADC的重要模块,其性能与整个接口电路的功能实现息息相关。基于哈尔滨工业大学微机电系统研究中心多年来致力于对陀螺接口电路的研究,本论文设计完成了一款应用于其中的2-1-1 MASH(Multi-stAge noise SHaping)结构ΣΔ调制器。本文在对国内外MASH调制器进行了调研的基础上,详细分析了调制器的工作原理以及不同结构的特点,采用Matlab对MASH调制器进行了系统建模和仿真分析,最终确定了设计的系统结构。此外,本文还将介绍系统中包含的非理想因素与最终设计结果之间的关系,对加入这些影响因子后的MASH结构系统进行系统建模和仿真。在系统建模的基础上,本文基于0.35 um 5V标准CMOS工艺完成了各个模块的电路级设计,并借助Cadence的spectre工具完成了各部分电路的功能验证。其中积分器选择了全差分双参考电压的开关电容结构,很好的抑制噪声;运放选取能够兼顾高增益和输出电压范围的两级套筒共源共栅形式;还完成了量化器、MOS互补开关、时钟电路以及数字抵消逻辑的设计。模拟和数字部分的功能均达到设计要求后,采用SpectreVerilog对数模混合电路进行了仿真,当输入信号带宽为10KHz,采样频率2.56MHz,得到最终所选MASH结构调制系统能达到的SNDR是103.86 dB,有效精度16.96 bits。最后,在华虹0.35 um CMOS工艺下完成了整体电路版图的绘制与后仿,并通过了DRC、LVS验证,版图的面积估算为2?um13952736。后仿系统能达到的SNDR是99.64 dB,有效精度16.26 bits。
[Abstract]:Digital silicon gyroscope interface circuit plays an important role in military field and daily life.However, the acquisition of continuous physical quantities in nature becomes a more easily operable discrete value, which is inseparable from the analog to digital converter (ADC), the medium. Sigma-Delta (危螖) modulator is also an important module of ADC. Its performance is closely related to the function realization of the whole interface circuit.Based on the research of gyroscope interface circuits in MEMS Research Center of Harbin University of Technology for many years, a 2-1-1 MASH(Multi-stAge noise SHaping-based 危螖 modulator is designed and implemented in this paper.Based on the investigation of the MASH modulator at home and abroad, the working principle of the modulator and the characteristics of different structures are analyzed in detail. The system modeling and simulation analysis of the MASH modulator are carried out by using Matlab.Finally, the system structure is determined.In addition, the relationship between the non-ideal factors contained in the system and the final design results will be introduced, and the system modeling and simulation of the MASH structure system with these influence factors will be carried out.On the basis of system modeling, the circuit level design of each module is completed based on 0.35um 5V standard CMOS process, and the functional verification of each part of the circuit is completed by means of spectre tool of Cadence.The integrator chooses the switch capacitor structure of fully differential double reference voltage, which can suppress noise very well; the operational amplifier selects the two-stage sleeve common grid form which can take into account the high gain and output voltage range; and the quantizer MOS complementary switch is also completed.Design of clock circuit and digital offset logic.After the functions of the analog and digital parts meet the design requirements, the digital-analog hybrid circuit is simulated by SpectreVerilog. When the input signal bandwidth is 10kHz and the sampling frequency is 2.56MHz, the SNDR of the final selected MASH modulation system is 103.86 dB and the effective precision is 16.96bit / s.Finally, the layout of the whole circuit has been drawn and simulated in the Huahong 0.35um CMOS process, and it has been verified by the DRCs. The area of the layout is estimated to be 2um 13952736.The SNDR of the post-simulation system is 99.64 dB and the effective precision is 16.26 bits.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN761

【参考文献】