基于SOI工艺FPGA中时钟管理模块的设计与验证

发布时间：2018-04-14 01:35

本文选题：时钟管理 + FPGA　；参考：《深圳大学》2015年硕士论文

【摘要】：自1985年第一块FPGA(Field-Programmable Gate Array)芯片面世至今只有30年的历史,但作为一个新兴产业,FPGA已经取得了辉煌的成就。目前,FPGA产品已从最初的通信设备扩展到控制、导航、航天、航空等各种军用、民用领域。作为一种可编程的ASIC(Application Specific Integrated Circuit),FPGA不仅克服了定制电路的诸多不足也解决了前几代可编程器件门电路数有限的问题,它已经成为数字系统设计的基础之一。时钟管理模块(DCM)是FPGA芯片的不可缺少的组成部分,DCM管理整个FPGA系统的时钟。时钟偏差和时钟抖动是电路系统中存在的主要问题,时钟管理模块能否正确工作直接影响FPGA的功能和性能,尤其是在高速运行的系统中。目前,系统的时钟管理方案一般基于锁相环或者延时锁相环电路。FPGA中时钟管理主要包括锁相环以及时钟分布网络。本文设计的时钟管理模块包括核心单元为全数字演示锁相环(ADDLL)以及与之相结合的时钟网络两个部分。按照每个模块实现的功能可分为锁定电路(主电路),移相电路(从电路),输出电路,时钟网络四个模块。锁定电路与移相电路都是由鉴相器、控制电路和延时电路等组成。系统工作时,主、从电路分工不同,从电路经过延时完成移相,生成相对相位为90°、180°、270°、360°的四个时钟信号。主电路实现输入时钟与从电路生成时钟其相位最接近信号的同步,实现输入时钟与芯片内部时钟的同步。输出电路除了能输出同步后的四个相位的时钟,还能输出时钟的多种分频信号及二倍频信号。
[Abstract]:It has been only 30 years since the first FPGA(Field-Programmable Gate chip was introduced in 1985, but it has made brilliant achievements as a new industry.At present, FPGA products have been extended from the original communication equipment to control, navigation, aerospace, aviation and other military, civil fields.As a programmable ASIC(Application Specific Integrated circuit, it not only overcomes many shortcomings of custom circuits, but also solves the problem of limited gate number of previous generations of programmable devices. It has become one of the foundations of digital system design.Clock management module (DCM) is an indispensable part of FPGA chip to manage the clock of the whole FPGA system.Clock deviation and clock jitter are the main problems in the circuit system. Whether the clock management module works correctly directly affects the function and performance of FPGA, especially in the high-speed system.At present, the clock management scheme of the system is based on PLL or DPLL circuit. The clock management in FPGA mainly includes PLL and clock distribution network.The clock management module designed in this paper includes two parts: the core unit is an all-digital demonstration phase-locked loop (ADDLL) and the clock network is combined with it.According to the function of each module, it can be divided into four modules: main circuit, phase shift circuit (slave circuit, output circuit, clock network).Lock circuit and phase-shift circuit are composed of phase detector, control circuit and delay circuit.When the system works, the main and slave circuits are divided into different parts, and the phase shift is completed by delay from the circuit to generate four clock signals with a relative phase of 90 掳(180 掳) and 270 掳(360 掳).The main circuit synchronizes the input clock with the phase closest to the signal generated from the circuit, and the input clock synchronizes with the internal clock of the chip.The output circuit can output not only the clock with four phases after synchronization, but also the frequency division signal and the double frequency signal of the clock.
【学位授予单位】：深圳大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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