基于TCAD三维器件模型仿真的电荷共享效应研究

发布时间：2018-04-15 03:28

本文选题：电荷共享 + SRAM单元　；参考：《电子科技大学》2015年硕士论文

【摘要】：随着集成电路制造工艺的发展,器件特征尺寸不断减小,器件间距也随之减小。当辐射环境中的高能粒子轰击半导体器件灵敏区域时,会在其敏感节点收集电荷,进而引发单粒子翻转效应或单粒子瞬态脉冲效应。当特征尺寸进入纳米级尺度时,电荷共享效应将成为该领域重要的可靠性问题之一。电荷共享不仅能导致存储单元发生多位翻转,还会使组合逻辑中产生多个单粒子瞬态脉冲,使系统的软错误率增加,从而加大抗辐射设计的难度。目前国内对电荷共享效应的研究主要集中于分立的MOS管之间,且主要考虑90 nm以上的工艺,并没有考虑存储单元和更小特征尺寸时电荷共享效应的影响或作用。因此,有必要从这些方面对电荷共享效应进行具体的研究分析,将其对电路的影响进行有针对性的加固。本文基于TCAD软件三维器件模型仿真,对40 nm CMOS工艺器件中的电荷共享效应做了深入的分析和研究,使用的SPICE模型为基于IBM 40 nm CMOS工艺模型。本文完成的主要研究工作包括:(1)40 nm工艺器件三维建模。通过查阅相关资料,建立了与IBM 40 nm CMOS工艺SPICE模型校准的晶体管三维器件模型。(2)不同因素对电荷共享效应的影响。研究了40 nm工艺中STI深度、粒子入射角度以及N型深阱的存在对电荷共享的影响。发现40 nm工艺中STI在500 nm时为抑制NMOS间电荷共享收集的有效深度;PMOS间电荷共享随STI增大呈线性下降;角度入射和N型深阱的引入会极大的增加NMOS间的电荷共享收集。(3)40 nm工艺中,电荷共享效应对单粒子瞬态(SET)脉宽和SRAM单元单粒子翻转(SEU)的影响。发现电荷共享的增加会抑制SET脉宽,并且在角度入射和三阱工艺中,SRAM单元会在电荷共享较大时发生翻转恢复。设计了新的版图结构,该结构可以充分利用NMOS间电荷共享,将不同NMOS间距时的翻转恢复阈值降低20%以上。(4)抑制电荷收集的方法研究。证明了90 nm工艺中常用的“保护漏”结构在40nm工艺中的不适用性。提出了新的抑制电荷单点收集和共享收集的附加电极结构,该结构将单点电荷收集量降低15%以上,使SRAM单元翻转阈值增大0.4 Me V·cm2/mg,并可以有效抑制NMOS间电荷共享和SRAMs发生MBU。
[Abstract]:With the development of IC manufacturing process, the characteristic size of the device decreases and the device spacing decreases.When the high-energy particles bombarded the sensitive region of semiconductor devices in the radiation environment, they would collect charges at their sensitive nodes, which would lead to the single-particle flip effect or the single-particle transient pulse effect.Charge sharing effect will become one of the important reliability problems in this field when the characteristic size reaches nanometer scale.Charge sharing can not only cause memory cells to flip, but also cause multiple single particle transient pulses in combinational logic, increase the soft error rate of the system, and increase the difficulty of anti-radiation design.At present, the research on the charge sharing effect is mainly focused on the discrete MOS transistor, and mainly considers the process above 90 nm, and does not consider the effect or action of the charge sharing effect when the memory cell and the smaller characteristic size are not taken into account.Therefore, it is necessary to study and analyze the charge-sharing effect from these aspects, and strengthen the effect on the circuit.Based on the 3D device model simulation of TCAD software, the charge-sharing effect in 40nm CMOS process is analyzed and studied in this paper. The SPICE model is based on IBM 40nm CMOS process model.The main research work in this paper includes the 3D modeling of the 40 nm process device.Based on the relevant data, the effect of different factors on the charge-sharing effect is established, which is calibrated with the SPICE model of IBM 40nm CMOS process.The effects of the depth of STI, the incident angle of particles and the existence of N-type deep well on the charge sharing in 40nm process are studied.It is found that the effective depth of STI for suppressing the collection of charge sharing between NMOS at 500nm decreases linearly with the increase of STI, and the incidence of angle and the introduction of N-type deep well will greatly increase the charge-sharing collection among NMOS at 40nm.The effect of charge sharing on the pulse width of single particle transient set and the single particle flip of SRAM unit.It is found that the increase of charge sharing can inhibit the pulse width of SET, and the flip recovery of SET cells occurs when the charge sharing is larger in the angle-incident and three-well processes.A new layout structure is designed, which can make full use of the charge sharing between NMOS to reduce the reverse recovery threshold of different NMOS spacing by more than 20%.It is proved that the "protection leakage" structure commonly used in 90 nm process is not applicable in 40nm process.A new additional electrode structure for suppressing charge collection and sharing collection is proposed. The structure reduces the charge collection by more than 15%, increases the flip threshold of SRAM cell by 0.4 me V cm 2 / mg, and can effectively inhibit the charge sharing between NMOS and the occurrence of SRAMs.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405

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