多通道高速采样系统的频率合成器实现技术研究

发布时间：2018-04-16 11:26

本文选题：频率合成器 + 2　；参考：《电子科技大学》2016年硕士论文

【摘要】：21世纪是高速发展的信息时代,电子技术的跨越式进步使得人们对电子产品的需求日益增长,而且性能要求越来越高。频率合成作为电子系统的重中之重,更是所有电子产品的最基本组成部分。高速采样系统在现代通信或是军事行业中运用广泛,采样时钟源作为采样系统的核心,其性能好坏决定了高速采样系统性能指标。因此,研究频率合成技术有相当重大的意义。本文主要设计了多通道高速采样系统中的作为采样时钟的频率合成器。首先分析了当今频率合成技术的种类,在理论上分析DDS和PLL的基本原理及其各自性能特点,在综合比较DDS和PLL各自优缺点,以及组合方案的优缺点后,结合系统指标要求,最终选择能使用多重调节因子,将DDS的高分辨率和高转换时间优点与PLL较好的杂散抑制性能和输出频率范围广的优点相结合的组合方案,DDS驱动PLL。设计的重点在于保证最终输出信号的精度条件下,使输出的采样时钟达到采样系统要求的杂散和相位指标,且输出频率范围较广。作者在本文中详细介绍了系统的各个关键器件的选型以及关键电路的绘制原则,并且设计实现了针对本次方案设计的降低系统杂散的多重调节算法,该算法通过筛选同一输出频率的不同参数组合来改善频率合成器最终输出信号的杂散性能,可以在满足高输出频率、高分辨率的前提下取得较好的杂散性能。最后对频率合成器进行实验测试,在论文最后对测试测试结果予以分析,最终经过实验结果验证,说明上述频率合成方法在实际应用中的可行性。本文主要提出并解决以下关键技术:1、针对项目需求给出频率合成器的性能指标,并给出了方案和器件选择原则。2、根据上述原则,设计出满足采样系统要求的频率合成器。3、结合频率合成器理论分析,实现了降低系统杂散的多重调节算法。
[Abstract]:The 21st century is an information age with rapid development. The leapfrog progress of electronic technology makes the demand for electronic products increasing day by day, and the requirement of performance is higher and higher.As the most important part of electronic system, frequency synthesis is the most basic component of all electronic products.High-speed sampling system is widely used in modern communications or military industry. Sampling clock source as the core of sampling system, its performance determines the performance of high-speed sampling system.Therefore, it is of great significance to study the frequency synthesis technology.In this paper, a frequency synthesizer used as a sampling clock in a multi-channel high-speed sampling system is designed.Firstly, the kinds of frequency synthesis techniques are analyzed, and the basic principles and performance characteristics of DDS and PLL are analyzed theoretically. After comparing the advantages and disadvantages of DDS and PLL, and the advantages and disadvantages of the combined scheme, the requirements of the system index are combined.Finally, we choose a combination scheme which combines the advantages of high resolution and high conversion time of DDS with the advantages of better spurious suppression performance and wide output frequency range of PLL.The emphasis of the design is to ensure the precision of the final output signal, so that the output sampling clock can reach the required spurious and phase index of the sampling system, and the output frequency range is wide.In this paper, the author introduces the selection of key devices and the principle of drawing key circuits in detail, and designs and implements a multi-adjustment algorithm to reduce the stray of the system.The algorithm can improve the spurious performance of the final output signal of the frequency synthesizer by screening different parameter combinations of the same output frequency, and can achieve better spurious performance under the premise of satisfying the high output frequency and high resolution.Finally, the frequency synthesizer is tested experimentally, and the test results are analyzed at the end of the paper. Finally, the feasibility of the frequency synthesizer is proved by the experimental results.This paper mainly proposes and solves the following key technology: 1, gives the performance index of the frequency synthesizer according to the requirements of the project, and gives the scheme and device selection principle .2. according to the above principles,A frequency synthesizer. 3, which meets the requirements of the sampling system, is designed. Combined with the theoretical analysis of the frequency synthesizer, a multi-adjustment algorithm to reduce the stray of the system is realized.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN74

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