一种抗总剂量CMOS电路基本结构研究

发布时间：2018-04-17 21:31

本文选题：总剂量效应 + 版图加固　；参考：《电子科技大学》2017年硕士论文

【摘要】：随着空间技术以及核工程技术的快速发展,越来越多的CMOS集成电路不可避免地应用于辐射环境中并受到各种辐射效应的影响,为了保证CMOS电路的可靠性和性能,抗辐照加固技术的研究始终面临着严峻的挑战。本文以一种抗总剂量CMOS电路基本结构为研究课题,提出一种抗总剂量基本晶体管结构,主要就其抗总剂量辐照能力以及其结构特性对抗总剂量能力的影响进行研究,并将其与传统的版图加固措施进行对比。本文基于总剂量效应的基本原理,深入研究总剂量辐照的物理过程以及总剂量效应对MOS器件电学特性参数的影响,从工艺和版图加固角度介绍目前业界常用的总剂量加固措施。基于总剂量的设计加固理念,本文提出一种抗总剂量基本晶体管结构,该结构通过在普通NMOS晶体管的源漏区外围形成P+掺杂区从而使得晶体管获得抗总剂量辐照的能力。接着本文使用Sentaurus TCAD软件平台仿真对比所提出的晶体管结构与普通的条栅NMOS晶体管,验证其总剂量加固的有效性,并在此基础上提出一种变形结构,丰富其应用范围。然后进一步研究对比所提出的晶体管结构及相应的变形结构和普通条栅NMOS晶体管随辐照剂量的变化,相应的性能退化趋势,并研究对比它们输出电流的差异。针对所提出的晶体管结构,本文继续更加深入地研究其结构特性对晶体管抗总剂量能力的影响。首先对比P+掺杂区有无直接连接到零电位两种情况下晶体管抗总剂量能力的差别,从而提出可以采用P+掺杂区无连接的方式来节省晶体管的版图布线资源,然后通过改变所提出晶体管的结构参数详细研究P+掺杂区浓度、宽度以及结深对晶体管抗总剂量能力的影响,接着研究P+掺杂区与N+源漏区的间距对晶体管的击穿电压和抗总剂量能力的影响。基于所提出的晶体管结构以及相应的变形结构属于总剂量版图加固措施的范畴,本文进一步将其与传统的版图加固措施进行对比。首先仿真对比所提出的晶体管结构与传统版图加固措施在抗总剂量能力方面的强弱,然后从基本门电路标准单元版图实现角度对比各个晶体管结构版图实现中的面积消耗情况,从而可以直观地衡量所提出的晶体管结构以及相应的变形结构在实际工程应用中的价值。
[Abstract]:With the rapid development of space technology and nuclear engineering technology, more and more CMOS integrated circuits are inevitably applied in radiation environment and affected by various radiation effects. In order to ensure the reliability and performance of CMOS circuits,The study of radiation-resistant reinforcement technology is always faced with severe challenges.In this paper, the basic structure of an anti-total dose CMOS circuit is taken as a research topic, and an anti-total dose basic transistor structure is proposed. The effects of its anti-total dose radiation ability and its structural characteristics against total dose ability are studied.And compare it with the traditional layout reinforcement measures.Based on the basic principle of total dose effect, the physical process of total dose irradiation and the effect of total dose effect on the electrical characteristic parameters of MOS devices are studied in this paper. From the point of view of technology and layout reinforcement, the measures commonly used in the field of total dose strengthening are introduced.Based on the design and reinforcement concept of total dose, this paper presents a structure of basic transistor against total dose, which makes the transistor gain the ability to resist total dose irradiation by forming P-doped region around the source and drain region of ordinary NMOS transistor.Then, we use the Sentaurus TCAD software platform to simulate and compare the proposed transistor structure with the ordinary stripe gate NMOS transistor, and verify the effectiveness of the total dose reinforcement. On this basis, a deformed structure is proposed to enrich its application range.Then we compare the proposed transistor structure with the corresponding deformed structure and the common stripe gate NMOS transistor with the radiation dose, the corresponding performance degradation trend, and compare the difference of their output current.In view of the proposed transistor structure, the influence of its structure characteristics on the total dose resistance of the transistor is further studied in this paper.First, the difference of the total dose resistance ability of the transistors with or without direct connection to the zero potential in the P-doped region is compared, and it is proposed that the layout and wiring resources of the transistors can be saved by using the connectionless method in the P-doped region.Then, by changing the structure parameters of the proposed transistor, the effects of the concentration, width and junction depth of the P-doped region on the total dose resistance of the transistor are studied in detail.Then the influence of the distance between the P doped region and the N source drain on the breakdown voltage and the total dose resistance of the transistor is studied.Based on the fact that the proposed transistor structure and the corresponding deformed structure belong to the category of total dose layout strengthening measures, this paper further compares them with the traditional layout strengthening measures.First, the strength of the proposed transistor structure is compared with that of the traditional layout reinforcement measures in terms of total dose resistance, and then the area consumption in the realization of each transistor structure layout is compared from the basic gate circuit standard cell layout realization point of view.Thus, the value of the proposed transistor structure and the corresponding deformed structure in practical engineering application can be measured intuitively.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN432

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