数字集成电路的防护软错误技术研究

发布时间：2018-04-17 22:21

本文选题：软错误 + 单粒子翻转　；参考：《安徽理工大学》2017年硕士论文

【摘要】：集成电路的工艺尺寸进入纳米级别后,软错误引起的可靠性问题已经成为数字电路的可靠性问题中不可忽视的问题之一。伴随着晶体管特征尺寸的缩小,锁存器对于高能粒子轰击其内部节点而产生的软错误变得愈加的敏感。本文提出一个低开销高性能的抗辐射锁存器结构设计。提出的锁存器结构使用了 C单元结构来防护单粒子翻转(SEU)并恢复被影响节点的逻辑值。在提出的锁存器结构中还使用了钟控门和功率门来提高性能。本文的主要工作如下:首先,简要的介绍了集成电路的发展历程和关于软错误的国内外的研究现状。其次,在了解集成电路的基础上开始深入的说明软错误的基本概念。在本章对单粒子效应进行了分类,其中对于单粒子翻转(SEU)和单粒子瞬态(SET)对集成电路的影响进行了详细的图解。第三部分是关于一些经典的锁存器结构的原理说明。在这部分会先介绍具有防护SEU能力的锁存器,然后是介绍具有防护SET能力的锁存器。在对这些锁存器的工作原理的分析的基础上还会指出其优缺点。最后是提出一个低开销高性能的锁存器结构设计。在本章节会详细论述提出的锁存器的结构、工作过程和防护软错误的原理。在后面部分,对提出的锁存器结构进行仿真实验验证并获取相关数据。在处理这些数据的基础上,对提出的锁存器结构分析其延迟、功耗和性能,通过和经典的锁存器结构的对比来查看提出的锁存器的优势所在。在同等的防护SEU能力下,提出的锁存器结构相较于FERST(feedback redundant SEU/SET-tolerant latch:反馈冗余方式容忍 SEU 和SET锁存器)锁存器,在延迟上减少了 46%,功耗上减少了 88.9%。在防护SET(Single Event Transient)的方面,提出的锁存器需要添加一个延迟单元来完成防护SET。通过HSPICE的仿真实验可以发现,提出的锁存器在各方面的性能都优于FERST锁存器。
[Abstract]:The reliability problem caused by soft errors has become one of the problems that can not be ignored in the reliability of digital circuits after the process size of integrated circuits reaches the nanometer level.As the characteristic size of transistors shrinks, latches become more sensitive to soft errors caused by high-energy particles bombarding their internal nodes.This paper presents a low cost and high performance anti-radiation latch structure design.The proposed latch structure uses the C unit structure to protect the single particle flip (SEU) and restore the logical values of the affected nodes.A clock gate and a power gate are also used to improve performance in the proposed latch structure.The main work of this paper is as follows: firstly, the development of integrated circuits and the research status of soft errors at home and abroad are briefly introduced.Secondly, the basic concept of soft error is explained in depth on the basis of understanding integrated circuit.In this chapter, the single particle effect is classified, in which the effects of single particle flip (set) and single particle transient (set) on the integrated circuit are illustrated in detail.The third part is about some classical latch structure principle explanation.This section introduces the latch with the ability to protect SEU and then the latch with the ability to protect the SET.Based on the analysis of the working principle of these latches, the advantages and disadvantages are also pointed out.Finally, a low cost and high performance latch structure is proposed.In this section, the structure of the latch, the working process and the principle of protection against soft errors are discussed in detail.In the latter part, the proposed latch structure is verified by simulation and relevant data are obtained.On the basis of processing these data, the delay, power consumption and performance of the proposed latch structure are analyzed, and the advantages of the proposed latch are compared with the classical latch structure.Compared with FERST(feedback redundant SEU/SET-tolerant latch (feedback redundancy tolerance SEU and SET latch) latch, the latch structure of the proposed latch reduces the delay by 46 and the power consumption by 88.9.In the aspect of protecting SET(Single Event transient, the latch proposed needs to add a delay unit to complete the protection of set.The simulation results of HSPICE show that the performance of the proposed latch is better than that of the FERST latch in every aspect.
【学位授予单位】：安徽理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN431.2

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