基于FPGA的高速串行数据采集及恢复技术研究

发布时间：2018-04-18 07:47

本文选题：时钟数据恢复 + LVDS　；参考：《电子科技大学》2017年硕士论文

【摘要】：随着高速串行通信系统的急速发展,对数据进行正确、高效地接收及恢复变得极为重要。过采样型时钟数据恢复电路具有结构简单、功耗较低的特点,随着工艺尺寸的减小,过采样型时钟数据恢复电路相对于其他时钟数据恢复电路结构,如被广泛应用的基于PLL型结构逐渐显示出两大优势:(1)过采样型时钟数据恢复电路无时钟相位反馈回路,相位锁定速度快(2)过采样型时钟数据恢复电路中有大量数字单元,面积小、成本低且系统便于移植。这些优势使过采样型时钟数据恢复电路在高速低功耗应用领域逐渐受到设计者的青睐。本文基于Xilinx 7系列FPGA平台,对过采样型时钟数据恢复电路的系统架构和关键模块单元进行了深入的研究和分析,并针对1Gbps LVDS信号设计了一个高速串行数据采集及恢复系统。文章首先分析了各种时钟数据恢复电路的基本结构,主要包括反馈相位跟踪型、过采样型和突发模式型。根据对电路结构的分析和实际应用平台,选取了过采样型时钟数据恢复电路结构作为系统的基本架构。根据传统过采样时钟数据恢复电路的原理,提出了设计所需的算法,包括过采样算法,边沿检测算法和数据恢复算法。完成算法设计后着重研究了如何使用Xilinx 7系列FPGA实现上述算法。本文设计的高速串行数据采集及恢复系统针对的是1Gbps高速串行数据,由于硬件平台的速率限制,传统的过采样结构无法在FPGA平台上实现。因此根据算法设计,将采样时钟和输入数据分别做复制和相移操作,利用两路具有相位差的采样时钟对复制后的两路数据进行过采样,并设计数据恢复模块实时跟踪系统的抖动情况,选择最优采样值。根据本文设计,采样时钟频率只需达到500MHz就可以实现对1Gbps输入信号的4X过采样,大大降低了过采样电路对硬件平台的运行速度要求。最后,在ISE开发平台中将HDL语言进行综合,得到系统的RTL级结构。并使用多种类型的输入信号对整个系统进行仿真验证。在仿真结果正确后,通过映射、布局布线、管脚分配等工作生成位流文件,将设计下载至FPGA中。最后通过对实际信号的采集及恢复验证系统的功能。仿真及测试结果表明:在输入信号速率达到1Gbps时,系统能够正常的实现数据采集及恢复功能,并且在多次采集及恢复的131072bit数据中均无误码产生。
[Abstract]:With the rapid development of high-speed serial communication system, it is very important to receive and recover data correctly and efficiently.The over-sampling clock data recovery circuit has the characteristics of simple structure and low power consumption. With the decrease of process size, the over-sampling clock data recovery circuit is compared with other clock data recovery circuit structures.For example, the widely used PLL structure gradually shows two major advantages: 1) the over-sampling clock data recovery circuit has no clock phase feedback circuit, and the phase locking speed is fast (2%) there are a large number of digital units in the over-sampling clock data recovery circuit.The area is small, the cost is low and the system is easy to transplant.These advantages make over-sampling clock data recovery circuit in high-speed and low-power applications gradually favored by designers.Based on Xilinx 7 series FPGA platform, the system architecture and key module units of over-sampling clock data recovery circuit are studied and analyzed in this paper. A high-speed serial data acquisition and recovery system is designed for 1Gbps LVDS signal.This paper first analyzes the basic structure of various clock data recovery circuits, including feedback phase tracking type, oversampling type and burst mode type.According to the analysis of the circuit structure and the practical application platform, the over-sampling clock data recovery circuit structure is selected as the basic structure of the system.According to the principle of the traditional over-sampling clock data recovery circuit, this paper presents the algorithms needed for the design, including over-sampling algorithm, edge detection algorithm and data recovery algorithm.After completing the algorithm design, this paper focuses on how to use Xilinx 7 series FPGA to realize the above algorithm.The high speed serial data acquisition and recovery system designed in this paper is aimed at 1Gbps high speed serial data. Because of the speed limitation of hardware platform, the traditional oversampling structure can not be realized on FPGA platform.Therefore, according to the algorithm design, the sampling clock and the input data are duplicated and phase-shifted respectively, and two sampling clocks with phase difference are used to oversample the two replicated data.The data recovery module is designed to track the jitter of the system, and the optimal sampling value is selected.According to the design of this paper, the 4X oversampling of 1Gbps input signal can be realized only when the sampling clock frequency is up to 500MHz, which greatly reduces the running speed of the oversampling circuit on the hardware platform.Finally, the RTL level structure of the system is obtained by synthesizing the HDL language in the ISE development platform.A variety of input signals are used to simulate the whole system.After the simulation results are correct, the design is downloaded to FPGA by mapping, routing and pin assignment.Finally, the function of the system is verified by collecting and recovering the actual signal.The simulation and test results show that when the input signal rate reaches 1Gbps, the system can normally realize the function of data acquisition and recovery, and there is no error code generation in the 131072bit data collected and recovered many times.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP274.2;TN791

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