14-bit 500MHz自校准电流舵DAC设计

发布时间：2018-04-19 17:48

本文选题：数模转换器 + 电流舵结构　；参考：《北方工业大学》2017年硕士论文

【摘要】：在这个信息快速传播的时代,由于在信号传播过程中对信号传输时传输速度/精度要求越来越高,为顺应这一发展趋势本文设计了精度为14-bit采样率500MHz的电流舵结构DAC。为了尽量降低一些非理想因素引起的偏差对动态性能的影响我们采用了一种随机选取校准算法来对bit10-bit14位电流源进行校准。本文采用中芯国际SMIC0.18um标准CMOS工艺进行设计,最终完成了一款带有数字校准的DAC设计并完成了以下主要任务和创新:(1)对输入信号采用bit1-bit5、bit6-bit9、bit10-bit14进行分段,然后对bit1-bit5 二进制译码,bit6-bit9、bit10-bit14 温度计译码。(2)在开关控制信号传输进入控制开关之前我们使用了限幅电路设计,通过该设计可以有效地降低信号交叉点与控制信号中的非理想信号的幅度从而降低输出信号中的毛刺。(3)对于bit10-bit14的电流源我们使用基于"数据比较"和"序列检测"随机选取算法对其进行数字校准。(4)在数字校准单元中,通过Verilog对算法进行功能实现、逻辑综合与物理层后端版图实现。在输入信号为1MHz采样频率为500MHz时,分别对不加校准和添加校准电路进行仿真,不加校准时SFDR为74.3634dB添加校准之后提高到78.2798dB。由仿真结果可以看出通过数字校准设计数模转换器动态特性得到显著提高。
[Abstract]:In this era of rapid information transmission, the speed / precision of signal transmission is becoming more and more high in the process of signal transmission. In order to comply with this trend, a current rudder structure with precision of 14-bit sampling rate 500MHz is designed in this paper.In order to minimize the influence of the deviation caused by some non-ideal factors on the dynamic performance, a random selection calibration algorithm is used to calibrate the bit10-bit14 potential current source.In this paper, the SMIC SMIC0.18um standard CMOS process is used to design a DAC with digital calibration, and the following main tasks and innovations are accomplished. The input signal is segmented with bit1-bit5bit6-bit6-bit10-bit14, and the input signal is divided into two parts: bit1-bit5, bit6-bit6-bit10-bit14, bit1-bit5bit6-bit6-bit10-bit14.Then we use the limiting circuit design to decode bit1-bit5 binary code bit6-bit9bit10-bit14 thermometer. 2) before the switch control signal transmissions into the control switch,This design can effectively reduce the amplitude of the signal intersection and the non-ideal signal in the control signal, thus reducing the burr in the output signal.) for the current source of bit10-bit14, we use "data comparison" and "sequence detection" for the current source of bit10-bit14."A random selection algorithm is used for digital calibration. 4) in the digital calibration unit,The algorithm is implemented by Verilog, logic synthesis and physical layer back-end layout.When the input signal is 1MHz sampling frequency of 500MHz, the uncalibrated and added calibration circuits are simulated respectively. When the input signal is uncalibrated, the SFDR adds calibration to 74.3634dB and increases to 78.2798 dB.The simulation results show that the dynamic characteristics of the digital-to-analog converter are greatly improved by digital calibration.
【学位授予单位】：北方工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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