24位Sigma-Delta ADC中降采样数字滤波器的研究与设计

发布时间：2018-04-23 10:19

本文选题：24位Sigma-delta模数转换器 + Sigma-delta调制器　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：本文开展了24位Sigma-delta ADC中降采样数字滤波器的研究与设计,研究工作从Sigma-delta调制器结构入手,通过ASIC数字电路设计流程完成一款输入信号256MHz输出1MHz位宽24的降采样数字滤波器,本文的主要工作内容有:1.Sigma-Delta ADC的基本原理和结构的研究。简单讨论了ADC的原理和结构,然后重点阐述Sigma-Delta ADC的工作原理、实现结构、关键技术以及性能指标。2.Sigma-delta ADC的基本原理结构和性能仿真分析。使用Matlab搭建四级单环1位CIFB(Cascade-of-Integrator-Feed-Back)结构的Sigma-delta调制器,根据ADC系统设计要求确定结构参数后,进行了系统仿真,调制器的输入频率为256MHz,过采样率为256,信噪比为123.5dB,精度达到了20.22bits。3.降采样数字滤波器基本原理与结构的设计研究。首先讨论了降采样数字滤波器的原理结构,然后根据原理分析设计一款24bit的降采样数字滤波器,采用三级级联结构,第一级为CIC抽取滤波器,用来实现主要信号抽取功能;第二级为CIC补偿滤波器,用来补偿CIC抽取滤波器的通带衰减,同时对信号实现2倍抽取;第三级为两个半带滤波器级联,用来调整滤波器的阻带衰减和过渡带带宽,同时也对信号实现4倍抽取。4.降采样数字滤波器的系统设计和仿真。输入信号频率256MHz,输出频率为1MHz,抽取倍数为256,采用Matlab中的Simulink工具建立降采样滤波器各级子模块并封装,对各级和系统分别进行仿真。5.降采样数字滤波器的ASIC实现。编写降采样数字滤波器的RTL代码和测试平台代码,在Modelsim中进行功能仿真,验证功能正确后,通过DC对代码进行逻辑综合得到门级网表,查看时序报告建立时间满足后将网表导入ICC中进行物理实现,实现过程包括Floorplan(布图规划)、Placement(标准单元摆放)、CTS(时钟树综合)、Route(绕线),绕线完毕之后通过Starrcc抽取寄生参数在PT中进行静态时序分析,保持时间都满足之后添加DFM的相关设置,保存得到降采样数字滤波器的GDS格式版图,在Carlibre中通过了DRC和LVS检查。本文的工作对高精度Sigma-delta ADC中的降采样数字滤波器的设计具有一定的借鉴意义。
[Abstract]:In this paper, the research and design of down-sampling digital filter in 24-bit Sigma-delta ADC is carried out. Starting with the structure of Sigma-delta modulator, a downsampling digital filter with input signal 256MHz output 1MHz bit width 24 is completed by ASIC digital circuit design flow. The main work of this paper is: 1. The basic principle and structure of Sigma-Delta ADC. This paper briefly discusses the principle and structure of ADC, and then focuses on the working principle, implementation structure, key technology and basic principle structure and performance simulation analysis of Sigma-Delta ADC. 2. Sigma-delta ADC. A four-stage single-ring Sigma-delta modulator with one bit CIFBN Cascade-of-Integrator-Feed-Back-structure is constructed by using Matlab. After determining the structural parameters according to the design requirements of the ADC system, the system simulation is carried out. The input frequency of the modulator is 256 MHz, the over-sampling rate is 256, the signal-to-noise ratio is 123.5 dB, and the precision is 20.22 bits.3. Design and Research on the basic principle and structure of De-sampling Digital filter. Firstly, the principle structure of demultiplexing digital filter is discussed, and then a demultiplexing digital filter of 24bit is designed according to the principle. It adopts three-stage cascade structure, the first stage is CIC decimation filter, which is used to realize the main signal decimation function. The second stage is a CIC compensation filter, which is used to compensate the passband attenuation of the CIC decimation filter, and the signal is decimated twice. The third stage is a cascade of two half-band filters, which is used to adjust the stopband attenuation and the transition band bandwidth of the filter. At the same time, the signal is 4 times decimated. System design and simulation of decimation digital filter. The input signal frequency is 256 MHz, the output frequency is 1 MHz, and the decimation multiple is 256. The down-sampling filter sub-modules are established and encapsulated by the Simulink tool in Matlab. ASIC implementation of decimated digital filter. The RTL code and the test platform code of the down-sampling digital filter are written, and the function simulation is carried out in Modelsim. After the function is verified correctly, the gate network table is obtained by logic synthesis of the code by DC. After viewing the time sequence report setup time is satisfied, the network table is imported into ICC for physical implementation. The implementation process includes the design of Starrcc (layout Planning) (CTS). After winding, the parasitic parameters are extracted by Starrcc to analyze the static time sequence in PT, and the relative setting of DFM is added after the holding time is satisfied. The GDS format layout of the decimated digital filter is saved, and the DRC and LVS are checked in Carlibre. The work in this paper can be used for reference in the design of decimated digital filter in high precision Sigma-delta ADC.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN713.7

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