功率LDMOS的静电防护设计改进

发布时间：2018-04-25 23:15

本文选题：静电放电 + 横向扩散金属氧化物半导体　；参考：《南京邮电大学》2016年硕士论文

【摘要】：随着半导体芯片的制造工艺不断改进以及特征尺寸的减小,集成电路日益向小型化和高密度化发展,很容易遭受到静电放电(ESD)的影响。一次轻微的ESD事件,甚至会造成器件永久失效。横向扩散金属氧化物半导体(Laterally Diffused Metal Oxide Semiconductor,LDMOS)作为常用的功率器件,具有较好的驱动能力,为了与现有的工艺相兼容,由LDMOS器件修改后的高压ESD防护器件可用作芯片管脚的ESD防护。本论文详细分析了LDMOS在ESD应力下的电学特性和热学特性,提出了两个新结构,并用仿真软件进行验证。主要的研究成果包括:1、深入分析了ESD产生的过程及各测试模型,对ESD防护器件受到静电脉冲后所涉及到的物理仿真模型进行了分析,主要包括物理传输方程、能带模型、迁移率、雪崩击穿模型、间接复合和俄歇复合。2、针对常规LDMOS器件在ESD应力下由于触发电压过高,表面电流集中而导致器件抗ESD性能不高的问题,提出并验证了一种用于降低表面电流集中的新结构,新结构通过引入具有高低掺杂浓度的漂移区和N型衬底埋层,具有了低触发电压,二次击穿电流高等优点。仿真结果表明:新结构触发电压降低了36%,二次击穿电流提高了51%。3、针对常规SCR-LDMOS器件开启触发电压过高、维持电压过低问题,提出一种利用PN结辅助开启的新结构。新结构通过引入PN结来辅助提高触发开启前的空穴载流子浓度,降低了触发电压,提高了维持电压,并且具有较强ESD鲁棒性。仿真结果表明:新结构触发电压降低了44%,维持电压提高了两倍多。
[Abstract]:With the continuous improvement of semiconductor chip manufacturing process and the reduction of characteristic size, the integrated circuit is becoming more and more miniaturized and high-density, which is vulnerable to the influence of electrostatic discharge (ESD). A minor ESD event can even cause permanent invalidation of the device. Laterally Diffused Metal Oxide Semiconductors LDMOS), as common power devices, have good driving capability. In order to be compatible with the existing technology, the modified high voltage ESD protective devices by LDMOS devices can be used as ESD protection for chip pins. In this paper, the electrical and thermal properties of LDMOS under ESD stress are analyzed in detail. Two new structures are proposed and verified by simulation software. The main research results include: 1, deeply analyzing the process of ESD generation and each test model, and analyzing the physical simulation model of ESD protective device after being subjected to electrostatic pulse, mainly including the physical transmission equation, energy band model. Mobility, avalanche breakdown model, indirect recombination and Auger recombination. 2. In view of the problem that the ESD resistance of conventional LDMOS devices is not high due to the high trigger voltage and surface current concentration under ESD stress. A new structure for reducing surface current concentration is proposed and verified. The new structure has the advantages of low trigger voltage and high secondary breakdown current by introducing drift region with high and low doping concentration and burying layer of N-type substrate. The simulation results show that the trigger voltage of the new structure is reduced by 36 and the secondary breakdown current is increased by 51. 3. Aiming at the problem of high trigger voltage and too low maintenance voltage in conventional SCR-LDMOS devices, a new structure assisted by PN junction is proposed. The new structure increases the carrier concentration of holes before trigger opening by introducing PN junction, reduces the trigger voltage and improves the maintenance voltage, and has strong ESD robustness. The simulation results show that the trigger voltage of the new structure is reduced by 44 and the maintenance voltage is increased by more than two times.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN386

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