一种面向功耗均衡逻辑的综合与布局布线方法

发布时间：2018-04-26 05:41

本文选题：功耗均衡 + 密码芯片　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：旁路攻击技术对密码芯片外部可测量的一些功耗、电磁场等旁路信息进行分析,绕过基于计算复杂度的密码安全问题,破解密码芯片的密钥。面对日益严峻的安全问题,对芯片防御技术的研究尤为重要。双轨功耗均衡是一种比较高效的抗功耗攻击方法。利用该方法实现的模块,其功耗取值与输入信号的翻转不具有相关性,从而较好地保持了功耗均衡性。由于双轨功耗均衡单元的结构与普通单端标准单元存在很大差异,现有的商业EDA工具不直接支持面向双轨逻辑的后端操作。为了能够最大限度的使用现有成熟的自动化工具对双轨逻辑进行后端操作,实现面向双轨单元模块的功耗均衡性,本文研究面向功耗均衡逻辑的综合与布局布线方法。主要工作如下:1、针对现有成熟的EDA工具不支持双轨逻辑的综合问题,提出了一种基于单元信息替换的逻辑综合方法。在进行逻辑综合时,将双轨库文件中的信息替换到单端标准库文件中,构建虚拟单端库文件。最大限度的使用现有成熟自动化工具实现双轨逻辑的综合。2、针对双轨单元信号的对称性布线问题,提出了一种基于宽线的布线方法。该方法采用自定义布线规则,使用成熟EDA工具进行宽线单轨布线。然后对布线结果的DEF(design exchange format)文件进行自动化脚本处理,将单轨信号线拓展为双轨信号线。最终形成对称的双轨布线版图数据。3、贯通了功耗均衡模块,从编写RTL级代码、逻辑综合到布局布线的半定制流程。提取了双轨单元的物理库文件与时序库文件。构建了逻辑综合和布局布线所需要的虚拟单端库。以AES算法中的power模块为例,验证了基于单元信息替换的综合方法和基于宽线的双轨布线方法的可用性。SPICE模拟结果表明:模块在不同输入下的电源电流波形几乎完全重合,且抗功耗攻击参数NED(Normalized Energy Deviation)为0.09834,达到较高的功耗均衡性。
[Abstract]:The bypass attack technology analyzes the power consumption electromagnetic field and other bypass information which can be measured outside the cipher chip bypassing the cryptographic security problem based on computational complexity and cracking the key of the cipher chip. In the face of increasingly serious security problems, the research of chip defense technology is particularly important. Dual-track power equalization is an efficient method to resist power attack. The power consumption of the module realized by this method is not related to the input signal flipping, so the balance of power consumption is well maintained. Because the structure of the dual-track power equalization unit is very different from that of the common single-ended standard cell, the existing commercial EDA tools do not directly support the back-end operation for dual-track logic. In order to maximize the use of existing mature automation tools for dual-track logic back-end operation, achieve dual-track unit module power balance, this paper studies the power equalization logic synthesis and layout routing method. The main work is as follows: 1. Aiming at the problem that the existing mature EDA tools do not support two-track logic, a logic synthesis method based on unit information replacement is proposed. In the process of logic synthesis, the information in the dual-track library file is replaced by the single-ended standard library file, and the virtual single-ended library file is constructed. In order to solve the problem of symmetrical routing of dual-track unit signals, a wideband routing method is proposed to realize the synthesis of two-track logic by using existing mature automation tools to the maximum extent. The method adopts custom routing rules and uses mature EDA tools for wide line monorail routing. Then, the DEF(design exchange format file of the routing result is processed automatically, and the monorail signal line is extended to double track signal line. Finally, the symmetrical double-track layout data. 3 is formed, and the power balance module is passed through. From writing the RTL level code, the logic synthesizes to the semi-custom flow of layout and routing. The physical library file and timing database file of dual track unit are extracted. The virtual single end library for logic synthesis and layout and routing is constructed. Taking the power module in the AES algorithm as an example, the availability of the synthesis method based on unit information replacement and the two-track routing method based on wide wire are verified. The simulation results show that the power current waveform of the module is almost completely overlapped under different input conditions. The anti-power attack parameter NED(Normalized Energy selection is 0.09834, which achieves high power equalization.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405

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