自动化流程在基带芯片XG726后端设计中的应用与实现

发布时间：2018-04-27 12:52

本文选题：自动化流程 + 等价性检验　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：近年来,通信终端芯片的发展十分迅速,但同时移动终端的设计却越来越困难。首先,随着CMOS工艺尺寸从90nm到65nm再到现在的28nm,其静态功耗已经大到可以和动态功耗比肩甚至更大的程度,所以降低芯片电源网络的静态功耗和动态功耗已经成为纳米级集成电路设计的重要课题之一。其次,随着集成电路工艺不断的发展,芯片的规模越来越大,使得芯片的验证也变得越来越困难,出现一些功能上的错误的概率也越来越大。因此如何减少验证时间,如何有效地修改错误,加快产品的上市时间将变得越来越重要。自动化流程正是在这个情况下得到了快速的发展。数字集成电路设计大体上可以分为前端设计和后端设计。前端设计一般是从RTL(寄存器传输级)代码设计到逻辑综合生成网表,后端设计就是通常指的是物理实现过程。然而数字后端设计由于它的复杂性以及设计周期较紧张的问题,往往决定着芯片能否及时流片成功(Taped Out),因此自动化流程有着广阔的应用空间。所谓的自动化流程就是将复杂的工具命令分解成数个步骤,每个步骤都用简单的命令实现,同时将每个步骤跑完产生的日志文件分别保存起来,这样既可以提升设计的效率,同时又可以方便设计人员对错误进行纠正。本论文基于数字基带芯片XG726,主要研究的是ECO(工程更改顺序)流程和低功耗流程。做ECO需要前后端设计人员的不断沟通,前端设计人员告诉后端设计人员在哪个模块需要做ECO,后端人员完成后又需要前端人员去验证是否实现了预期的功能。通过ECO流程可以较快地修改在后仿真发现的电路功能性问题,同时针对不同的模块采用不同的ECO流程来得到合理的补丁大小,从而极大地降低了后端物理实现的难度。新的ECO流程方法主要包括打平(Flatten)ECO流程以及断点(Cut Point)ECO流程。打平ECO流程主要是逻辑综合带来的边界优化的问题,而断点ECO流程适用于组合逻辑链长的网表。除ECO流程外,所做的工作还包括在PCIE模块搭建并测试标准UPF流程(Golden UPF Flow)将结果和旧的流程(Base Flow)进行比较,判断新的流程在结果上是否更优。而对于Verdi-SignOff流程,因为这是一个新的用于检测功耗意图的工具,并没有老的流程可以借鉴,因此需要在环境中搭建,并且编辑相关的输入文件,同时评测它在检测结果是否更优。总而言之,这两个流程可以大大提高低功耗设计的效率,并且Verdi-SignOff这个工具和MVRC(多电压域规则检查)相比在性能上有了极大的提升。论文所提出的有关流程的实现方法和需要注意的问题,全部来自于数字后端设计的相关经验,具有良好的参考价值。
[Abstract]:In recent years, the development of communication terminal chip is very rapid, but at the same time, the design of mobile terminal is becoming more and more difficult. First, with the size of the CMOS process from 90nm to 65nm to the current 28nm, the static power consumption is so large that it can be compared with dynamic power consumption even more. Therefore, reducing the static and dynamic power consumption of chip power network has become one of the most important issues in the design of nanoscale integrated circuits. Secondly, with the continuous development of integrated circuit technology, the scale of the chip becomes larger and larger, which makes the verification of the chip become more and more difficult, and the probability of some functional errors becomes more and more large. Therefore, how to reduce the verification time, how to modify errors effectively, and how to speed up the time to market will become more and more important. It is in this context that automation processes are rapidly developed. Digital integrated circuit design can be divided into front-end design and back-end design. The front-end design is generally from RTL (register transfer level) code design to the logic synthesis generation network table. The back-end design usually refers to the physical implementation process. However, due to its complexity and tight design cycle, the digital back-end design often determines whether the chip can flow successfully in time, so the automation process has a wide application space. The so-called automation process is to decompose complex tool commands into several steps, each step is implemented with a simple command, and the log files generated by each step are saved separately, which can enhance the efficiency of the design. At the same time, it is convenient for designers to correct errors. Based on the digital baseband chip XG726, this paper mainly studies the ECOF (Engineering change order) process and the low power consumption process. To do ECO requires continuous communication between front and rear designers. The front-end designers tell the back-end designers which module they need to do ECO.The back-end designers need front-end staff to verify whether or not they have achieved the desired function. The functional problems found in the post-simulation can be quickly modified by ECO process, and the reasonable patch size can be obtained by using different ECO processes for different modules, which greatly reduces the difficulty of physical implementation of back-end. The new ECO process methods mainly include the leveling and flattening eco process and the breakpoint cut Point)ECO process. Leveling ECO process is mainly a problem of boundary optimization brought by logic synthesis, while breakpoint ECO process is suitable for net table with length of combinational logic chain. In addition to the ECO process, the work includes setting up and testing the standard UPF UPF flow in the PCIE module, comparing the result with the old one, and judging whether the new flow is better or not. For the Verdi-SignOff process, because it is a new tool for detecting the power consumption intention, there is no old process to learn from it, so it needs to be built in the environment, edit the relevant input files, and evaluate whether it is better in detecting results. In a word, these two processes can greatly improve the efficiency of low power design, and the performance of Verdi-SignOff is greatly improved compared with that of MVRC (Multi-Voltage Domain Rule checking). The implementation methods and problems that need to be paid attention to are all from the relevant experience of digital back-end design, which has good reference value.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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