基于FPGA的RFIC测试平台的硬件电路设计与实现

发布时间：2018-04-27 18:13

本文选题：RFIC + 测试平台　；参考：《东南大学》2015年硕士论文

【摘要】：随着无线通信技术的发展,射频芯片的性能变得尤为重要,高效、可靠的测试成为设计中一个不可缺少的环节。本文基于这样的背景,结合国内外在芯片测试方面的研究现状,设计了一种通用的测试平台,该平台包括待测件、测试板、PC机和测试仪器。本文的主要工作是完成测试平台的硬件电路设计,包括FPGA控制基板的设计、电源设计和基带电路设计。设计的难点在于保证基带信号在测试平台上的性能,使之传输性能受硬件电路的影响达到最小,因此本文在保证测试平台功能的基础上,对基带信号进行了优化。基带信号在测试平台上以模拟差分对的形式连接待测器件和转换器,测试板上的外围电路会在差分对上产生共模噪声,对基带信号造成影响,从而影响测试平台的可靠性。本文首先分析了共模噪声产生的原因,然后对滤波系统等效阻抗网络进行建模分析,得出阻抗不匹配会影响共模噪声向差模信号的转换。本文在硬件电路上设计一种平衡结构的共模滤波器对基带信号进行优化设计,该滤波器采用对称的滤波网络,设计中考虑了PCB走线及元件的寄生参数对阻抗的影响,该共模滤波器能在最大程度抑制差分对中的共模噪声,从而保证基带信号的质量。最后,本文对测试平台进行了验证。根据实测差分信号优化前后的眼图对比可知,共模噪声减小了0.12V,测试平台的基带发射信号SNR提升了2dB,基带接收信号SNR提升了3dB。另外,对系统待测件控制性能的测试结果表明,测试板可以提供多路自由可调的电源信号,且电源负载电流可测。动态测试所需的可调10电平转换时间为0.836μs,达到了设计要求。时钟幅度、频率、频偏和抖动都满足设计指标。
[Abstract]:With the development of wireless communication technology, the performance of RF chips becomes more and more important. Based on this background and the current research situation of chip testing at home and abroad, a general test platform is designed in this paper. The platform consists of a test piece, a test board, a PC and a test instrument. The main work of this paper is to complete the hardware circuit design of the test platform, including the design of FPGA control substrate, power supply and baseband circuit design. The difficulty of the design is to ensure the performance of the baseband signal on the test platform, so that the transmission performance is minimized by the hardware circuit. Therefore, this paper optimizes the baseband signal on the basis of guaranteeing the function of the test platform. The baseband signal is connected to the device and converter in the form of analog differential pair on the test platform. The peripheral circuit on the test board will produce common mode noise on the differential pair, which will affect the baseband signal, thus affecting the reliability of the test platform. In this paper, the causes of common-mode noise are analyzed at first, and then the equivalent impedance network of filtering system is modeled and analyzed. It is concluded that impedance mismatch will affect the conversion of common-mode noise to differential mode signal. In this paper, a balanced common-mode filter is designed to optimize the baseband signal in hardware circuit. The filter adopts a symmetrical filter network, and the influence of the parasitic parameters of the PCB line and the element on the impedance is considered in the design. The common-mode filter can suppress the common-mode noise in the differential pair to the maximum extent, thus ensuring the quality of the baseband signal. Finally, the test platform is validated. According to the comparison of the measured differential signals before and after optimization, the common mode noise is reduced by 0.12 V, the baseband transmit signal SNR is increased by 2 dB, and the baseband receiving signal SNR is increased by 3 dB. In addition, the test results show that the test board can provide multiple free and adjustable power signals, and the load current of the power supply can be measured. The adjustable 10 level conversion time required for dynamic testing is 0.836 渭 s, which meets the design requirements. Clock amplitude, frequency, frequency offset and jitter all meet the design specifications.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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