Turbo乘积码低复杂度译码算法的研究与FPGA实现

发布时间：2018-04-28 21:25

本文选题：Turbo乘积码 + Chase算法　；参考：《电子科技大学》2017年硕士论文

【摘要】：随着无线通信技术的迅猛发展,信息传输的可靠性问题越来越引起人们重视,关于信道编码技术的研究也越来越多。Turbo乘积码作为一种编码效率高、纠错性能好的线性分组码,有着巨大的研究价值和应用潜力,近些年成为了信道编码领域的研究热点。然而,Turbo乘积码传统的Chase迭代译码算法复杂度较大,不太适合硬件实现。因此,如何改进Chase迭代译码算法以取得译码性能和复杂度的合理折中成为了Turbo乘积码的研究重心。本文围绕Turbo乘积码编译码技术展开,研究并选定了一种低复杂度译码算法,然后基于该算法进行了译码器的硬件设计及FPGA实现。全文研究内容主要包括以下方面:1.在系统阐述Turbo乘积码编译码原理的基础上,深入研究了Chase迭代译码算法及其改进的低复杂度算法,并仿真分析了原始算法和改进算法的性能差异。本文采用的低复杂度改进Chase迭代译码算法在610-误码率下能够获得6.8dB以上的编码增益。2.对本文选定的低复杂度Chase迭代译码算法进行了硬件设计及FPGA实现,并通过功能仿真对设计的译码器电路进行了功能上的验证。在主要误码率区间上,功能仿真相比浮点仿真的码块编码增益差在0.1dB以内。3.基于Altera DE5-Net FPGA开发平台进一步对设计的译码器电路进行了验证及性能分析。本文设计的Turbo乘积码译码器硬件资源使用率较低,最大工作时钟频率为333MHz,可完成最高33Mbps速率的码块实时译码,具有最低248?s的译码延时。研究和实现表明,本文采用的Turbo乘积码低复杂度译码算法及据此设计的译码器满足了课题需求。
[Abstract]:With the rapid development of wireless communication technology, people pay more and more attention to the reliability of information transmission. As a linear block code with high coding efficiency and good error-correcting performance, there are more and more researches on channel coding. It has great research value and application potential. In recent years, it has become a research hotspot in the field of channel coding. However, the traditional Chase iterative decoding algorithm for turbo product codes is more complex and less suitable for hardware implementation. Therefore, how to improve the Chase iterative decoding algorithm to achieve a reasonable compromise between decoding performance and complexity has become the focus of the study of Turbo product codes. In this paper, a low complexity decoding algorithm is studied and selected around the Turbo product code encoding and decoding technology, and then the hardware design and FPGA implementation of the decoder are carried out based on the algorithm. The main contents of this paper include the following aspects: 1. 1. On the basis of systematically expounding the principle of Turbo product code encoding and decoding, the Chase iterative decoding algorithm and its improved low complexity algorithm are studied in depth, and the performance differences between the original algorithm and the improved algorithm are simulated and analyzed. In this paper, the improved Chase iterative decoding algorithm with low complexity can obtain the coding gain above 6.8dB at 610-bit error rate (BER). Hardware design and FPGA implementation of the low complexity Chase iterative decoding algorithm selected in this paper are carried out, and the functional verification of the designed decoder circuit is carried out by functional simulation. Compared with floating-point simulation, the gain difference of code block coding in the main bit error rate range is within 0.1dB. 3. Based on Altera DE5-Net FPGA development platform, the designed decoder circuit is verified and its performance is analyzed. The Turbo product decoder designed in this paper has a low utilization rate of hardware resources and a maximum working clock frequency of 333MHz. It can complete the block real-time decoding with the highest 33Mbps rate and has the lowest decoding delay of 248s. The research and implementation show that the low complexity decoding algorithm of Turbo product codes and the decoder designed in this paper meet the requirements of the subject.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22;TN791

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