65nm工艺下6.25Gbps SerDes发送器的设计

发布时间：2018-04-29 15:40

本文选题：SerDes + 信道衰减　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：随着通信技术的不断提升,数据传输量大大提高,为了在尽量短的时间内传递更多的信息,需要大幅度提升传输速率。当数据传输速率达到Gbps以上之后,传输线上的衰减加剧,数据间的干扰更加严重,误码率不断提高。传统的并行数据已不能满足高速数据之间的传输的需求,但是新型串行链路传输方式却能满足这种高速传输的需求。SerDes作为一种典型的串行数据传输方式,其研究越来越得到重视。本文基于65nm工艺,在研究SerDes发送器的理论基础上设计了一款速率能够达到6.25Gbps的Ser Des发送器。该发送器的输入为20位的并行数据,输出为一对差分的数据,输出数据带有0-9.6dB可编程预加重功能。本文的主要工作分为以下几点:1)分析比较三种并串转换电路结构的优缺点,结合本文设计发送器需要满足的传输速率,设计了在低速情况下使用移位寄存器型并串转换结构和在高速情况下使用CML结构的并串转换电路;2)设计并实现了占空比调节电路保证在整个并串转换过程中使用的时钟的占空比为50%;3)设计并实现了可编程预加重驱动器,最大能够弥补9.6dB的信道损耗,能够有效的消弱前标和后标码间干扰;4)设计接收端检测电路来检测接收端是否存在;本文设计了SerDes发送器的电路、版图,对设计的电路和版图做了详尽的仿真,得到仿真结果完全满足PCIE2.0的协议要求。发送器输出的数据速率能够达到6.25Gbps、5Gbps、3.125Gbps、2.5Gbps和1.25Gbps;输出数据幅值能够实现0.8-1.2V可调;输出数据眼图的眼高满足要求,左右张开能够达到0.9UI;jitter小于0.1UI。
[Abstract]:With the continuous improvement of communication technology, the amount of data transmission is greatly increased, in order to transfer more information in as short a time as possible, it is necessary to greatly improve the transmission rate. When the data transmission rate reaches above Gbps, the attenuation on the transmission line increases, the interference between the data becomes more serious, and the bit error rate increases continuously. The traditional parallel data can not meet the needs of high-speed data transmission, but the new serial link transmission mode can meet the demand of high-speed transmission. SerDes is a typical serial data transmission mode. More and more attention has been paid to its research. Based on the 65nm process, a Ser Des transmitter with the rate of 6.25Gbps is designed on the basis of studying the theory of SerDes transmitter. The input of the transmitter is 20 bit parallel data, the output data is a pair of difference data, the output data has 0-9.6dB programmable preweighting function. The main work of this paper is divided into the following points: 1) analyzing and comparing the advantages and disadvantages of the three parallel series conversion circuit structures, combining with the design of the transmitter in this paper to meet the transmission rate. In this paper, we design and implement the shift register type parallel string conversion circuit at low speed and the parallel string conversion circuit with CML structure at high speed. (2) the duty cycle adjusting circuit is designed and implemented to ensure the use of the circuit in the whole process of parallel string conversion. Designed and implemented a programmable pre-emphasis driver The maximum can compensate for the channel loss of 9.6dB, and can effectively reduce the pre-standard and post-code inter-symbol interference (4) the design of the receiver detection circuit to detect the existence of the receiver; this paper designed the SerDes transmitter circuit, layout, The designed circuit and layout are simulated in detail, and the simulation results fully meet the requirements of PCIE2.0 protocol. The output data rate of the transmitter can reach 6.25Gbps-5Gbps-3.125Gbps-2.5Gbps and 1.25Gbps.The output data amplitude can be adjusted 0.8-1.2V, and the eye height of the output data can meet the requirements, and the left and right opening can reach 0.9U Ijitter less than 0.1UI.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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