安全SOC芯片AES算法模块的设计与实现

发布时间：2018-04-30 19:45

本文选题：SOC芯片 + AES算法　；参考：《辽宁大学》2015年硕士论文

【摘要】：随着信息安全变得日益重要,高级加密标准(Advanced Encryption Standard,AES)被越来越广泛的使用。本文研究的主要目的是如何减少AES硬件实现的硬件消耗。本文介绍了AES算法的原理以及硬件实现方法,并且为了减少AES的硬件消耗,提出了一系列的优化方法,这些方法的设计与实现是本文的主要工作也是主要的闪光点。其中包括:半等效解密算法,加解密资源共享,S-BOX的合成域实现,加解密时密钥的实时产生,列混合变换的字节级设计,行变换优化。本文通过分析直接解密算法和等效解密算法的优缺点,最终采用半等效解密算法,最大实现加解密的资源共用;通过有限域的性质以及合成域的相关知识,实现了用逻辑实现的加解密共用的S-BOX;由于现在大多数密钥产生及使用的方法是将密钥一次性提前扩展后存储,以实现加解密共用,此方法会浪费大量的存储资源,所以本文详细的介绍了如何实时的去扩展并输出每轮加解密所需的密钥,实现了资源的优化;列混合变换的加解密所需的系数差别很大,所以大多数设计会设置两套单独的列混合变换,本文详细的介绍了如何在Byte级去设计列混合变换,使加解密共用一套列混合变换;另外本文通过分析行移位变换的加密与解密结果,优化了行移位变换。通过本文介绍的优化及设计方法,可以实现AES加密算法的硬件实现并做到显著的优化。其中,寄存器的数量降低到了原设计的25%,门数降低到了原设计的50%。
[Abstract]:As information security becomes more and more important, Advanced Encryption Standard AESs are becoming more and more widely used. The main purpose of this paper is to reduce the hardware consumption of AES hardware implementation. This paper introduces the principle of AES algorithm and hardware implementation method, and in order to reduce the hardware consumption of AES, a series of optimization methods are proposed. The design and implementation of these methods is the main work of this paper is also the main flash point. These include: semi-equivalent decryption algorithm, implementation of S-BOX synthesis domain, real-time generation of key during encryption and decryption, byte level design of column mixed transformation, and optimization of row transformation. By analyzing the advantages and disadvantages of the direct decryption algorithm and the equivalent decryption algorithm, this paper uses the semi-equivalent decryption algorithm to maximize the resource sharing of encryption and decryption. The S-BOX-based encryption and decryption sharing implemented by logic is implemented. Because most of the key generation and usage methods are stored in advance after the key is expanded in advance, so as to realize encryption and decryption sharing, this method will waste a lot of storage resources. Therefore, this paper introduces in detail how to extend and output the key needed for each round of encryption and decryption in real time, and realize the optimization of resources. So most design will set two separate column mixed transformation, this paper introduces how to design column mixed transform in Byte level, so that encryption and decryption share a set of column mixed transformation; In addition, by analyzing the encryption and decryption results of line shift transform, the line shift transform is optimized. Through the optimization and design method introduced in this paper, the hardware implementation of AES encryption algorithm can be realized and significant optimization can be achieved. The number of registers is reduced to 25 and the number of gates is reduced to 50.
【学位授予单位】：辽宁大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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