基于FPGA的图像超分辨率的硬件化实现

发布时间：2018-05-01 04:38

本文选题：FPGA + 超分辨率　；参考：《现代电子技术》2017年17期

【摘要】：设计基于FPGA的图像超分辨率双线性插值实现方式,提出基于单输入双输出端口RAM缓冲的二级循环调度机制,用以实现共享资源分配和并行流水处理。单输入双输出端口的RAM实现读取相邻地址的两个数据,RAM的深度为源图像一行的像素点数,宽度为像素数据宽度,实现源数据相邻两行像素的存储。根据位置分析模块得到源图像的位置,将源图像的数据写入相应RAM中进行加权运算。为了提高效率使用乒乓算法,设计了4个RAM,2个RAM为一组,一组RAM在加权运算时,另一组RAM写入数据。该设计在Kintex-7开发板上得到验证,实现图像处理速度达到25~30 f/s,同时图像插值后不仅细节更加清晰,从直方图中可以看到图像得到了均衡化。
[Abstract]:An image super-resolution bilinear interpolation scheme based on FPGA is designed, and a two-stage cyclic scheduling mechanism based on single input and double output port RAM buffer is proposed to achieve shared resource allocation and parallel pipelining. The RAM of single input and double output port can realize the storage of two adjacent rows of source data. The depth of the RAM is the pixel number of one row of the source image and the width of the width of the data is the width of the pixel data. According to the position analysis module, the location of the source image is obtained, and the data of the source image is written into the corresponding RAM for weighted operation. In order to improve the efficiency of using ping-pong algorithm, we designed four Ram, two RAM as a group, one group of RAM in the weighted operation, the other group of RAM to write data. The design is verified on the Kintex-7 development board, and the speed of image processing is up to 2530 f / s. After image interpolation, not only the details are more clear, but also the image is equalized from the histogram.
【作者单位】：南京铁道职业技术学院;中电科技德清华莹电子有限公司;南京航空航天大学;
【基金】：国家自然科学基金面上项目(51475240) 航空科学基金自由探索类项目(2014ZD52053) 江苏省轨道交通控制工程技术研究开发中心开放基金(KFJ1509)
【分类号】：TN791;TP391.41

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