6位高速CMOS数模转换器集成电路的研究和设计

发布时间：2018-05-03 16:02

本文选题：数模转换器(DAC) + 电流舵　；参考：《东南大学》2015年硕士论文

【摘要】：数模转换器(DAC)作为数字系统到模拟系统的一个重要接口,越来越受到人们的重视。近年来通信技术尤其是无线通信技术的快速发展,对DAC转化速率的要求也越来越高。高速DAC的性能在某种程度上成为了高速通信系统性能的瓶颈之一。因此研究和设计高速DAC芯片具有重要的现实意义。论文首先介绍了DAC的工作原理和重要指标。接着分析了电阻型、电容型和电流舵三种类型DAC的各自特点和实现方式。电流舵架构由于其将电流源的电流直接输出到负载不需要任何缓冲这一固有特性使得其在高速DAC中得到广泛应用。基于此,本文详细分析和讨论了影响电流舵DAC静态特性和动态特性的关键因素。分析了电流源阵列的随机失配项并定量给出了电流源尺寸的选取方案,介绍了减小系统失配的布局方案。推导了电流源阻抗与静态特性和无杂散动态范围(SFDR)的定量关系并分析了共源共栅电流源的输出阻抗随频率的变化趋势。所设计的6位高速DAC基于65rnmCMOS工艺,采用高四位温度计译码和低两位二进制加权的4+2电流舵结构。整个电路包括模拟和数字两大部分。模拟部分主要提供所需要的电流源。通过采用内置的带隙电压基准源产生稳定电压,进而通过电压转电流电路和电流镜来获得稳定的电流源。内置的电流源较好地保证了精度和集成度。数字部分主要为译码器和为了保证各路信号同步性的译码前后的寄存器和锁存器。对译码器的设计做了精细的考虑,通过优化逻辑结构以及门单元电路并在其中插入缓冲器来使得译码器能正确处理高速信号并将各路信号之间的延时控制在一定范围内。为了在转换过程中电流源阵列始终提供稳定的电流,译码后的控制信号通过调制器产生一个高交叉点的差分控制信号来控制差分开关的断开与闭合。这样使得在切换过程中差分开关不存在同时关断的现象。本设计完成了原理图设计,版图设计和后仿真。其总面积为0.675mm×0.485mm。芯片采用1.2V单电源供电,整个功耗小于20mW。后仿真结果表明具有良好的静态和动态特性,其DNL,INL均小于0.05LSB。在8GHz时钟频率作用下,输出信号频率在2.7GHz内SFDR大于34dB；在5GHz时钟频率作用下,整个奈奎斯特带宽SFDR大于42dB。
[Abstract]:As an important interface between digital system and analog system, DAC is paid more and more attention. In recent years, with the rapid development of communication technology, especially wireless communication technology, the requirement of DAC conversion rate is becoming higher and higher. The performance of high-speed DAC has become one of the bottlenecks of high-speed communication system to some extent. Therefore, the research and design of high-speed DAC chip has important practical significance. This paper first introduces the working principle and important index of DAC. Then, the characteristics and implementation methods of resistive type, capacitance type and current rudder are analyzed. The current rudder architecture is widely used in high speed DAC because it outputs the current directly to the load without any buffer. Based on this, the key factors affecting the static and dynamic characteristics of the current rudder DAC are analyzed and discussed in detail. The random mismatch of the current source array is analyzed and the selection scheme of the current source size is given quantitatively. The layout scheme to reduce the system mismatch is introduced. The quantitative relationship between current source impedance and static characteristics and no stray dynamic range (SFDR) is derived and the variation trend of output impedance with frequency is analyzed. Based on the 65rnmCMOS process, the six-bit high-speed DAC is designed with a high four-bit thermometer decoding and a low-two-bit binary weighted 42 current rudder structure. The whole circuit includes two parts: analog and digital. The analog part mainly provides the needed current source. The stable voltage is generated by using the built-in bandgap voltage reference source, and then the stable current source is obtained by voltage-to-current circuit and current mirror. The built-in current source ensures the accuracy and integration. The digital part is mainly a decoder and registers and latches before and after decoding to ensure the synchronization of each signal. The design of the decoder is carefully considered. By optimizing the logic structure and the gate circuit and inserting a buffer in it, the decoder can process the high speed signal correctly and control the delay between the various signals within a certain range. In order to provide a stable current during the conversion process, the decoded control signal generates a high intersection differential control signal through the modulator to control the opening and closing of the differential switch. In this way, the differential switch does not turn off at the same time in the switching process. This design completes the schematic design, layout design and post-simulation. Its total area is 0.675mm 脳 0.485mm. The chip uses 1.2V single power supply, and the whole power consumption is less than 20mW. The simulation results show that it has good static and dynamic characteristics, and its DNL INL is less than 0.05 LSBs. Under the action of 8GHz clock frequency, the output signal frequency is greater than 34dB in 2.7GHz, and the whole Nyquist bandwidth SFDR is more than 42 dB under 5GHz clock frequency.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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