数字下变频的设计与实现

发布时间：2018-05-05 00:24

本文选题：数字下变频 + CORDIC算法　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：软件无线电是无线通信的创新形式,并将推动着无线通信领域的不断创新。随着软件无线电的快速发展,该技术广泛应用于军事和民用通信等领域,数字下变频技术作为其关键技术之一,逐渐成为研究的焦点。FPGA是高速可配置的逻辑电路,具有可编程性、灵活性和高集成性等特点。基于FPGA实现数字下变频,符合软件无线电的灵活开放要求。本文综合考虑FPGA设计中的性能与成本的问题,结合数字下变频算法原理,采用级联方式,根据每级的算法特点,设计数字下变频的高效实现结构。本文主要研究内容如下:本文基于数字下变频原理及其功能,完成了数字下变频的RTL级设计,并进行了功能验证及逻辑综合。首先,在多速率信号处理、CORDIC算法、DA算法和特殊滤波器算法等理论的基础上,根据数字下变频原理及其功能进行系统规划,将其划分为两个大模块:下变频模块和抽取滤波器组模块。然后,基于CORDIC算法设计了具有并行流水线结构的下变频模块,通过一系列移位相加运算,同时完成了数控振荡器产生正余弦波样本和混频器的相乘功能,该结构数据吞吐量大,节省了查找表和两个并行乘法器。最后,依据抽取理论和多相分解技术,结合抽取滤波器组模块中各个模块的算法特点,完成了抽取滤波器组模块中CIC抽取滤波器模块、CIC补偿滤波器模块、HB滤波器模块和FIR滤波器模块的设计。其中,根据易位变换和Nobel恒等式原理,将CIC抽取滤波器模块中的抽取操作放在积分器部分和梳状滤波器部分之间,梳状滤波器部分工作在较低的时钟频率下,所需的延迟单元数量显著减少;利用滤波器系数对称性,采用DA算法结合抽取结构来实现CIC补偿滤波器模块,采用DA算法结合多相结构来实现HB滤波器模块,这两种结构先进行抽取,再进行滤波运算,避免了不必要的运算,有效提高了运算效率;FIR滤波器模块采用串并结合的DA算法结构来实现,该结构节约了硬件资源,并且提高了运算速度。本论文采用MATLAB和Modelsim对设计的RTL级的数字下变频进行功能验证。其中,下变频模块中的CORDIC模块计算正余弦函数的精度达到10-5数量级。将数字下变频的处理结果与MATLAB模型的处理结果进行对比,其相对误差值达到10-5数量级,该精度满足设计要求。本文采用Synopsys公司的综合工具Design Compiler,在SMIC 65nm的标准工艺库下,对数字下变频进行了逻辑综合,该数字下变频的最大工作时钟频率为290.698MHz,综合面积为99496.800420μm2。本设计具有可移植性,便于进行系统的功能扩展和升级,有一定的研究参考价值。
[Abstract]:Software radio is an innovative form of wireless communication, and will promote the continuous innovation in the field of wireless communication. With the rapid development of software radio, this technology is widely used in military and civil communication fields. As one of its key technologies, digital down conversion technology has gradually become the focus of research. FPGA is a high speed configurable logic circuit. It has the characteristics of programmability, flexibility and high integration. Digital down conversion based on FPGA meets the flexible and open requirement of software radio. In this paper, the performance and cost of FPGA design are considered synthetically. Combining with the principle of digital down-conversion algorithm, the efficient realization structure of digital down-conversion is designed according to the algorithm characteristics of each stage by cascading method. The main contents of this paper are as follows: based on the principle and function of digital down conversion, the RTL level design of digital down conversion is completed, and the function verification and logic synthesis are carried out. Firstly, on the basis of the theory of multi-rate signal processing Cordic algorithm and special filter algorithm, the system planning is carried out according to the principle and function of digital down-conversion. It is divided into two modules: downconversion module and decimation filter bank module. Then, based on the CORDIC algorithm, a downconversion module with parallel pipeline structure is designed. By a series of shift addition operations, the numerical control oscillator produces the multiplication function of sinusoidal wave samples and mixers, and the data throughput of the structure is large. Save lookup table and two parallel multipliers. Finally, according to the decimation theory and the polyphase decomposition technology, combined with the algorithm characteristics of each module in the decimation filter bank module, The design of CIC decimation filter module and FIR filter module in decimation filter bank is completed. According to the principle of translocation transformation and Nobel identity, the decimation operation in the CIC decimation filter module is placed between the integrator part and the comb filter part, and the comb filter part works at a lower clock frequency. The number of delay units required is significantly reduced, the CIC compensation filter module is realized by using DA algorithm combined with decimation structure, and the HB filter module is implemented by DA algorithm combined with polyphase structure. These two kinds of structures are extracted first, then filtered to avoid unnecessary operation, and the efficiency of the Fir filter module is effectively improved by using the series-parallel DA algorithm structure, which saves the hardware resources. And the operation speed is improved. In this paper, MATLAB and Modelsim are used to verify the function of RTL level digital downconversion. Among them, the CORDIC module in the downconversion module can calculate the sinusoidal function with a precision of 10-5 orders of magnitude. The results of digital down-conversion are compared with those of MATLAB model. The relative error reaches 10-5 orders of magnitude, and the precision meets the design requirements. In this paper, we use Design Compiler, a synthetic tool of Synopsys Company, to synthesize the digital down-conversion under the standard process library of SMIC 65nm. The maximum working clock frequency of the digital down-conversion is 290.698MHz, and the synthetic area is 99496.800420 渭 m ~ 2. The design is portable, easy to expand and upgrade the system, and has a certain reference value.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN92;TN713

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