基于时间数字转换的硅通孔绑定前测试方法

发布时间：2018-05-09 16:14

本文选题：可测试性设计 + 内建自测试　；参考：《中国科学:信息科学》2017年02期

【摘要】：硅通孔中的缺陷不仅会导致硅通孔网络中传输延迟变化,也会引起对故障更为敏感的跳变延迟波动.本文基于时间数字转换原理提出一种非侵入式、皮秒级精度的绑定前硅通孔测试方法来检测电阻开路故障和泄漏故障.把硅通孔看作是驱动门的容性负载,遍历环状缩减单元的脉冲将会一直被缩减,直到该脉冲消失.将脉冲的缩减量数字化成一个数字码并与预期无故障信号的数字码进行比较.使用HSPICE在45 nm CMOS集成电路工艺库下模拟故障检测实验.实验结果表明本文方案能够检测到0.2 k?以上的电阻开路故障和等效泄漏电阻40 M?以下的泄漏故障.与现有方案相比,本文方案测试精度可以达到皮秒级,具有更大的故障检测范围以及质量分级能力,对初始输入信号频率或测试时钟信号频率无严格限制,可测试性设计面积开销相比于晶片面积可以忽略不计.
[Abstract]:The defects in the through hole not only lead to the change of the transmission delay in the through hole network, but also cause the fluctuation of the jump delay which is more sensitive to the fault. Based on the principle of time-digital conversion, a non-invasive, picosecond precision pre-binding silicon through hole testing method is proposed to detect open circuit and leakage faults of resistance. The silicon through hole is regarded as the capacitive load of the drive gate, and the pulse of the traversing ring reduction unit will be reduced until the pulse disappears. The reduced pulse is digitized into a digital code and compared with the expected fault-free digital code. HSPICE is used to simulate the fault detection experiment in 45 nm CMOS integrated circuit process library. The experimental results show that the proposed scheme can detect 0.2 k? Above resistance open circuit fault and equivalent leakage resistance 40m? The following leak failure. Compared with the existing scheme, the test precision of this scheme can reach picosecond level, it has larger fault detection range and quality classification ability, and there is no strict limitation on the initial input signal frequency or test clock signal frequency. The testability design area overhead is negligible compared to the wafer area.
【作者单位】：安徽财经大学计算机科学与技术系;安徽财经大学电子信息工程系;
【基金】：国家自然科学基金(批准号:61274036,61371025,61474036,61540011,31601224) 安徽省高校省级自然科学研究重点项目(批准号:KJ2016A001,KJ2016A006,KJ2014A005) 安徽省自然科学基金青年项目(批准号:1608085QF145)资助
【分类号】：TN406

【相似文献】