基于功耗独立的抗DPA攻击电路设计

发布时间：2018-05-12 11:36

本文选题：差分功耗分析(DPA) + 物理不可克隆函数(PUF)　；参考：《宁波大学》2017年硕士论文

【摘要】：随着信息安全和集成电路技术的不断发展,以密码芯片为核心部件的便携式设备在日常生活中得到广泛应用,如网上银行、智能卡等,给人们的生活提供了许多便利。然而,密码芯片在处理不同数据时,其能量消耗、运行时间和电磁辐射等物理信息与所处理的数据具有相关性。于是,攻击者通常利用这些物理信息对密码芯片实施旁道攻击(Side Channel Attack,SCA)可获取密钥信息。在一系列旁道攻击技术中,差分功耗分析(Differential Power Analysis,DPA)技术是一种常见且简单高效的旁道攻击方法,已经严重威胁到密码芯片的信息安全。因此各类抗DPA攻击的功耗独立技术应运而生,本文主要研究物理不可克隆函数(Physical Unclonable Functions,PUF)电路和灵敏放大型逻辑(Sense Amplifier Based Logic,SABL)电路,实现高效的防御DPA攻击。PUF电路是芯片领域的“DNA特征识别技术”,通过提取芯片复杂的物理特性产生无限多个唯一的、随机的和不可预测的密钥,实现输出数据只与工艺偏差有关,与功耗无关。SABL电路是一种动态双轨预充电路,其通过引入预充电技术使电路输出具有恒定的翻转率,从而具有功耗恒定的特性,理论上可以完全消除电路功耗与所处理数据的相关性。研究内容主要包含以下几个部分:1.基于电桥失衡效应的PUF电路设计:首先通过对电桥失衡效应的分析,结合PUF电路的设计特点,将由于工艺偏差所导致失衡的四臂电桥作为偏差信号产生电路,从而得到两路随机偏差电压,然后利用电压型灵敏放大器比较输入的偏差电压大小,产生输出信号,进而实现具有高随机性的PUF电路。2.基于单稳态定时偏差的PUF电路设计:首先分析单稳态定时电路的自我标识物理特性及失配情况,提出长定时单稳态电路设计方法,然后利用该单稳态电路产生定时偏差信号以及激励信号控制数据选择器选择两个定时偏差信号,结合SR仲裁器判决输出信号,最终实现具有高识别性的PUF电路。3.基于SABL的抗DPA攻击可重构加法器设计:通过对传统超前进位加法器原理的研究,根据SABL电路工作特点设计出具有抗DPA攻击性能的4位超前进位加法器电路,然后利用该4位超前进位加法器电路构成16位可重构超前进位加法器电路,实现支持4个8位数据或2个16位数据的加法运算电路。4.基于SABL的抗DPA攻击移位寄存器设计:通过对传统移位寄存器和SABL单元电路原理的研究,根据主从触发器的原理设计具有清零置位功能的D触发器电路,然后利用该触发器电路及SABL逻辑门实现能够防御差分功耗分析、具有左移右移并入并出功能4位移位寄存器电路。本文所提出的电路方案均采用TSMC 65nm CMOS工艺参数设计,并利用Spectre等工具对电路进行仿真验证。结果表明所设计的电路逻辑功能正确,相关性能指标有明显的优化。
[Abstract]:With the development of information security and integrated circuit technology, portable devices based on cipher chips have been widely used in daily life, such as online banking, smart cards and so on. However, when the cipher chip processes different data, its physical information, such as energy consumption, running time and electromagnetic radiation, is correlated with the processed data. Therefore, attackers usually use these physical information to carry out bypass attack on cryptographic chip side Channel attack (SCA) to obtain key information. Among a series of bypass attack techniques, differential Power Analysis (DPA) is a common and simple and efficient bypass attack method, which has seriously threatened the information security of cryptographic chips. Therefore, various power independent techniques against DPA attacks have emerged. In this paper, we mainly study physical Unclonable functions (PUFs) circuits and sense Amplifier Based logic (SABLs) circuits. The efficient protection against DPA attack. PUF circuit is the "DNA feature recognition technology" in the chip field, which generates infinite unique, random and unpredictable keys by extracting the complex physical characteristics of the chip. The output data is only related to the process deviation, and the power consumption independent. SABL circuit is a kind of dynamic dual track precharge circuit. By introducing precharge technology, the output of the circuit has a constant turnover rate, which has the characteristic of constant power consumption. Theoretically, the correlation between circuit power consumption and the data processed can be completely eliminated. The research mainly includes the following parts: 1. PUF circuit design based on bridge imbalance effect: firstly, through the analysis of bridge imbalance effect, combined with the design characteristics of PUF circuit, the four-arm bridge which is out of balance due to process deviation is used as the bias signal generation circuit. Two random bias voltages are obtained, and then the input bias voltage is compared with the voltage source sensitive amplifier to generate the output signal, and then the high randomness PUF circuit. 2. Design of PUF Circuit based on Monostable timing deviation: firstly, the self-identification physical characteristics and mismatch of Monostable timing circuit are analyzed, and the design method of long time Monostable Circuit is proposed. Then, two timing bias signals are selected by using the Monostable circuit and the excitation signal control data selector, and finally the highly recognizable PUF circuit. 3 is realized by combining with the SR arbiter decision output signal. The design of reconfigurable adder against DPA attack based on SABL: through the study of the principle of traditional carry adder, according to the working characteristics of SABL circuit, a 4-bit carry-adder circuit with anti-DPA attack performance is designed. Then the 4-bit carry-ahead adder circuit is used to construct the 16-bit reconfigurable carry-ahead adder circuit, which supports four 8-bit data or two 16-bit data. The design of anti-DPA attack shift register based on SABL: by studying the traditional shift register and the principle of SABL cell circuit, according to the principle of master-slave flip-flop, the D-flip-flop circuit with zero setting function is designed. Then the flip-flop circuit and the SABL logic gate are used to implement the differential power analysis, and the four-bit shift register circuit with the function of left shift and right shift merging and output function is realized. In this paper, TSMC 65nm CMOS process parameters are used to design the circuit, and Spectre is used to verify the circuit. The results show that the logic function of the designed circuit is correct and the related performance indexes are obviously optimized.
【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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