集成电路形式化验证的FPGA加速技术研究

发布时间：2018-05-12 15:41

本文选题：现场可编程门阵列 + 集成电路验证　；参考：《广西民族大学》2015年硕士论文

【摘要】：模拟和混合信号电路已经广泛应用于电子消费、电通讯、电子医疗等很多领域。但是,在深亚微米设计中,物理效应可能会破坏常见的数字抽象化后的电路行为。本文采用混杂系统的方法对模拟和混合信号电路模型进行形式化的验证。提出了电路级验证的形式化方法,此方法是基于变迁验证问题的可达性分析问题,利用非线性常微分方程的改进节点分析模型对电路的动力学行为建模,计算从给定初始状态向前探索能达到的所有可能的电路行为。模拟电路行为的性质确保完全正确的发现设计的缺陷。并针对由非线性常微分方程建模的电路系统的验证需求,提出了一种新的集成电路形式化验证的硬件方法,采用FPGA作为硬件加速部件,加速Coho形式化验证算法的计算。采用Sysgen工具重新改写Coho形式化验证算法,将Coho形式化验证算法的求解变成对应的硬件电路的设计问题,通过设计合适的硬件完成形式化验证的计算。实验结果表明,与Coho验证算法的软件执行时间相比,硬件实现可以获得10倍左右的性能加速。本研究能够进一步扩展Coho的应用领域,尤其是扩展到以前因为计算性能无法应用的领域。
[Abstract]:Analog and mixed signal circuits have been widely used in many fields, such as electronic consumption, electric communication, electronic medicine and so on. However, in deep submicron design, physical effects may destroy common digital abstracting circuit behavior. In this paper, the hybrid system method is used to formalize the simulation and mixed signal circuit models. A formal method of circuit level verification is proposed, which is based on the reachability analysis of transition verification problem. The improved node analysis model of nonlinear ordinary differential equation is used to model the dynamic behavior of the circuit. Calculate all possible circuit behaviors that can be achieved from a given initial state forward. The nature of analog circuit behavior ensures the correct detection of design defects. Aiming at the verification requirement of the circuit system modeled by nonlinear ordinary differential equations, a new hardware method for formal verification of integrated circuits is proposed. FPGA is used as the hardware acceleration component to accelerate the calculation of the formal verification algorithm of Coho. The formal verification algorithm of Coho is rewritten by using Sysgen tool, and the solution of the formal verification algorithm of Coho is transformed into the design problem of corresponding hardware circuit, and the calculation of formal verification is accomplished by designing appropriate hardware. The experimental results show that compared with the software execution time of the Coho verification algorithm, the hardware implementation can achieve about 10 times faster performance. This study can further extend the application of Coho, especially to areas where computing performance can not be applied in the past.
【学位授予单位】：广西民族大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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