片上网络部分关键链路故障的诊断与容错技术研究

发布时间：2018-05-15 12:54

本文选题：3D + NoC　；参考：《合肥工业大学》2016年硕士论文

【摘要】：3D NoC是将3D技术与片上网络相结合,集合了可扩展性强、集成度高、功耗低、延迟低等优点。3D NoC的通信节点、资源节点通过互连线连接成为一个巨大的网络。互连线包括router与router之间、IP核与router之间的普通数据链路,芯片与芯片之间垂直连接的TSV,还有一种特殊的互连线是指NoC测试外壳的旁路。因为工艺的不成熟,互连线容易在制造和使用的过程中出现故障。为保证3D NoC芯片的正常通信,本文为部分关键的数据链路的测试与容错进行了深入研究。为了解决3D NoC中的通信问题、TSV失效、互连线短路等问题,需要对网络中的互连线路进行测试。而3D IC的测试技术已经成为3D芯片设计与制造的掣肘。如何避免TSV复杂测试结构的可靠性问题、保证TSV测试的正确性已经成为一个关键问题。本文中提出一种类似反弹机制的新的测试结构,通过在上下层添加硬件机制对TSV增加新的自测试结构,使我们能够很方便的测出当前TSV是否故障,再通过冗余的TSV对TSV的故障进行容错。本文中提出的新的结构不需要复杂的硬件设备和上下两层的频繁交互,本文使用DC对测试结构的面积进行仿真,使用pspice对功耗进行仿真,实验结果表明本文中提出的测试结构需要较小的面积开销,和较低的功耗。目前采用IEEE 1500测试外壳的方法可以一定程度上解决NoC路由器测试的问题,但当测试外壳的旁路出现一个及以上的故障时,很可能导致一整条扫描链上的NoC路由器测试失败。针对该问题,本文通过提出一个深度优先最短路径算法得到从固定的扫描输入端到扫描输出端的最短路径,并通过提出的递归划分逐步求精法对路径进行筛选分块排序,构造多条扫描测试链将整个网络中的路由器分开测试。本文给出了测试外壳旁路故障的诊断和容错方法,使用节点分类测试方法实现对NoC路由器旁路故障的定位,并通过本文提出的测试外壳结构实现对故障旁路的容错。实验证明本文提出的算法和结构可以有效对测试外壳故障情况进行诊断,提高路由测试成功的可靠性,并且有效提高芯片的制造良率。
[Abstract]:3D NoC is a communication node which combines 3D technology with on-chip network and integrates the advantages of strong expansibility, high integration, low power consumption, low delay and so on. The resource node is connected into a huge network through interconnection. The interconnect includes a common data link between the IP core and the router between router and router, a vertical connection between the chip and the chip, and a special interconnection refers to the bypass of the NoC test shell. Because of the immaturity of the process, the interconnect is prone to malfunction in the process of manufacture and use. In order to ensure the normal communication of 3D NoC chip, this paper makes a deep research on the test and fault tolerance of some key data links. In order to solve the communication problems in 3D NoC, such as failure of NoC and short circuit of interconnection line, it is necessary to test the interconnection lines in the network. The testing technology of 3D IC has become a constraint in the design and manufacture of 3D chips. How to avoid the reliability problem of TSV complex test structure and ensure the correctness of TSV test has become a key problem. In this paper, a new testing structure is proposed, which is similar to the rebound mechanism. By adding a new self-test structure to the TSV by adding the hardware mechanism to the upper and lower layers, we can easily detect whether the current TSV is failing or not. Then the fault tolerance of TSV is carried out by redundant TSV. The new structure proposed in this paper does not require complex hardware and frequent interaction between the upper and lower layers. In this paper, DC is used to simulate the area of the test structure, and pspice is used to simulate the power consumption. The experimental results show that the proposed test structure requires less area overhead and lower power consumption. At present, the method of using IEEE 1500 to test the shell can solve the problem of NoC router testing to some extent, but if one or more faults occur in the bypass of the test shell, it may lead to the test failure of the NoC router on the whole scan chain. In order to solve this problem, we propose a depth-first shortest path algorithm to get the shortest path from the fixed scan input to the scanning output. Construct multiple scan test chains to test routers in the whole network separately. In this paper, the fault diagnosis and fault tolerance method of the test shell bypass is presented. The node classification test method is used to locate the bypass fault of the NoC router, and the fault tolerance of the fault bypass is realized through the structure of the test shell proposed in this paper. The experimental results show that the proposed algorithm and structure can effectively diagnose the fault of the test shell, improve the reliability of the successful routing test, and improve the manufacturing yield of the chip.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN47

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