基于UVM的高清晰图像传输芯片（DVLINK）的模块验证与研究

发布时间：2018-05-16 08:25

本文选题：UVM + 覆盖率　；参考：《广东工业大学》2016年硕士论文

【摘要】：随着深亚微米半导体工艺和超大规模数字集成电路设计的迅速发展,芯片集成度的提高给集成电路设计带来越来越多的挑战。在芯片的开发周期中,验证占了整个开发周期的大部分比例,甚至超过了芯片的设计时间。验证研究一直以来都是业界的重要研究课题,验证方法学的理论一直在革新和提高。UVM (Universal Verification Methodology)验证方法学综合AVM、OVM、VMM等多种验证方法学的优点,基于UVM验证方法学搭建灵活和可重用的验证平台,极大地提高了芯片验证的效率。本文研究来源于某微电子公司的实际项目,论文主要阐述了基于UVM验证平台的搭建及其在高清晰图像传输芯片(DVLINK)模块中的应用及研究。具体研究内容如下：首先是UVM验证平台的搭建。通过分析UVM验证方法学的演变,研究UVM验证平台的基本架构及其主要组件的特点,采用System Verilog验证语言描述各个UVM验证组件,通过抽象事务级建模搭建可重用的DVLINK验证平台。其次是DVLINK模块功能验证设计。采用覆盖率为导向进行功能验证设计,详细分析被测模块的Spec,提炼测试点并制定验证目标,研究黑盒测试、白盒测试等主流测试方法。此外,文章还进一步研究模型检测,采用混合测试的方式进行模块功能验证,并实现验证目标。最后总结了UVM验证平台设计结论。UVM验证平台的灵活性和可重用性特点,显著提高了DVLINK模块的验证效率,无需大范围改动数据,方便验证工程师的验证工作。基于VCEGAR的模型测试并自动生成验证报告,简单清晰的验证报告,提高验证的准确性。提取DVLINK模块的测试点并通过覆盖率目标。
[Abstract]:With the rapid development of deep submicron semiconductor technology and VLSI design, the improvement of IC integration level brings more and more challenges to IC design. In the chip development cycle, verification accounts for most of the whole development cycle, and even exceeds the chip design time. Verification research has always been an important research topic in the industry. The theory of verification methodology has been innovating and improving. Based on UVM verification methodology, a flexible and reusable verification platform is built, which greatly improves the efficiency of chip verification. The research in this paper comes from the actual project of a microelectronics company. This paper mainly describes the construction of UVM verification platform and its application and research in the high definition image transmission chip DVLINK module. The specific research contents are as follows: firstly, the UVM verification platform is built. By analyzing the evolution of UVM verification methodology, the basic architecture of UVM verification platform and the characteristics of its main components are studied. Each UVM verification component is described by System Verilog verification language, and a reusable DVLINK verification platform is built by abstract transactional modeling. Secondly, the function verification design of DVLINK module is introduced. The function verification design is based on coverage, the Specs of the tested module are analyzed in detail, the test points are refined and the verification goal is formulated, and the mainstream testing methods such as black box test and white box test are studied. In addition, the model detection is further studied, and the module function verification is carried out by mixed test, and the verification goal is achieved. Finally, the paper summarizes the design conclusion of UVM verification platform. The features of flexibility and reusability of DVLINK verification platform are summarized. The verification efficiency of DVLINK module is improved significantly, and the verification work of verification engineer is convenient without changing the data in a wide range. Model test based on VCEGAR and automatic generation of verification report, simple and clear verification report, improve the accuracy of verification. Extract the test points of the DVLINK module and pass the coverage target.
【学位授予单位】：广东工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402

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