低电压超低功耗人工耳蜗植入体芯片设计

发布时间：2018-05-18 07:00

本文选题：人工耳蜗 + 低电压　；参考：《华中科技大学学报(自然科学版)》2017年09期

【摘要】：基于台积电TSMC 0.35μm 3.3V标准半导体工艺,完成一款低电压、超低功耗人工耳蜗植入体芯片设计与流片.首先,基于目标工艺设计一套2.0V低电压标准单元库,完成电路结构设计、特征化提取和版图设计;其次,以2.0V低电压标准单元库为目标工艺库,完成植入体芯片综合及物理设计,引入基于蒙特卡罗仿真的统计静态时序分析方法,提高低电压路径的时序收敛性.测试结果显示:当工作电压由3.3V降至2.0V时,人工耳蜗植入体芯片功能正常,全芯片功耗下降了74.7%.
[Abstract]:Based on TSMC 0.35 渭 m 3.3V standard semiconductor technology, a low-voltage and ultra-low power chip for cochlear implant was designed and fabricated. First of all, based on the target process design, a set of low voltage standard cell library of 2.0 V is designed to complete the circuit structure design, feature extraction and layout design. Secondly, the 2.0 V low voltage standard cell library is taken as the target process library. In order to improve the timing convergence of low voltage path, a statistical static timing analysis method based on Monte Carlo simulation is introduced to complete the synthesis and physical design of implants. The test results show that when the working voltage is reduced from 3.3 V to 2.0 V, the function of the cochlear implant chip is normal, and the power consumption of the whole chip is reduced by 74.7%.
【作者单位】：厦门理工学院光电与通信工程学院;中国科学院微电子研究所;
【基金】：国家自然科学基金资助项目(61306093)
【分类号】：TN402

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