连续时间Sigma-Delta调制器建模与电路研究

发布时间：2018-05-19 03:32

本文选题：模数转换器 + Sigma-Delta调制器　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着通信系统发展,下一代无线通信系统的信道带宽需要扩展至几十甚至上百兆赫兹,并且动态范围不变。在此条件下,对ADC提出宽带、低功耗、高精度等要求。Sigma-Delta((50)(35))ADC作为这一领域的研究热点,与奈奎斯特采样ADC相比,具有更低功耗、更大动态范围和更高量化精度等优点。连续时间型Sigma-Delta ADC具有天然抗混叠滤波特性,并且对环路滤波器模块中运放的建立时间没有严格要求,这些优势使其适用于高速高精度转换领域且功耗更低。本文对连续时间Sigma-Delta ADC的关键模块Sigma-Delta调制器展开研究工作。首先分析比较前馈式与反馈式调制器的STF特性,结合两种结构的优点和不足提出一种混合式Sigma-Delta调制器。之后利用Matlab SD Toolbox设计工具,根据脉冲不变原理综合出连续时间Sigma-Delta调制器的传输函数H(s)。为了达到降低系统功耗的目的,本文采用无源RC积分器作为环路滤波器的第二级积分器,同时将补偿环路延时的零阶反馈环路前移并取消加法器,在信号带宽为10 MHz、OSR为16条件下,利用Matlab仿真得到调制器的SNDR为68.6 dB,SNR为68.6 dB,SFDR为100.9 dB,有效位数为9.5 bits。考虑到实际电路中存在多种非理想因素,本文分别分析系统中的运放有限增益带宽积、积分常数变化、环路延时和比较器失调等非理想因素。利用Smulink平台,针对非理想因素对系统整体性能影响,进行行为级建模仿真。采用零阶反馈环路吸收环路延时,采用NRZ反馈脉冲波形抑制时钟抖动,采用电容调谐阵列校准积分常数波动,采用DWA算法改进多比特量化器失配。最后在已通过行为级验证的三阶连续时间Sigma-Delta调制器系统结构基础上,展开电路分析与设计。采用SMIC 0.18?m 1P6M工艺,电源电压1.8 V,10 MHz信号带宽OSR为16的条件下对其仿真得到SFDR为98.4 dB,SNR为81.1 dB,SNDR为80.9 dB,有效位数为11.2 bits。
[Abstract]:With the development of communication system, the channel bandwidth of the next generation wireless communication system needs to be extended to tens or even hundreds of megahertz, and the dynamic range is invariant. Under this condition, the requirement of wideband, low power consumption and high precision is proposed for ADC. Sigma-Delta-50 ADC is a research hotspot in this field. Compared with Nyquist sampling ADC, it has the advantages of lower power consumption, larger dynamic range and higher quantization accuracy. Continuous time Sigma-Delta ADC has the characteristics of natural anti-aliasing filtering and has no strict requirements for the time of establishing operational amplifier in the loop filter module. These advantages make it suitable for high speed and high precision conversion and lower power consumption. In this paper, the key module of continuous time Sigma-Delta ADC (Sigma-Delta ADC), Sigma-Delta modulator, is studied. Firstly, the STF characteristics of feedforward and feedback modulators are analyzed and compared, and a hybrid Sigma-Delta modulator is proposed combining the advantages and disadvantages of the two structures. Then the transfer function of continuous time Sigma-Delta modulator is synthesized by using Matlab SD Toolbox design tool according to the principle of pulse invariance. In order to reduce the power consumption of the system, the passive RC integrator is used as the second stage integrator of the loop filter. At the same time, the zero-order feedback loop which compensates the loop delay is moved forward and the adder is cancelled. Under the condition that the signal bandwidth is 10 MHz OSR is 16, the SNDR of the modulator is 68.6 dB Matlab and the effective bit number is 9.5 bits. The SNR of the modulator is 68.6 dB SFDR is 100.9 dB, and the effective bit number is 9.5 bits. Considering that there are many non-ideal factors in practical circuits, this paper analyzes the non-ideal factors, such as limited gain bandwidth product, integral constant change, loop delay and comparator offset, respectively. Based on the Smulink platform, the behavior level modeling and simulation are carried out in view of the influence of non-ideal factors on the overall performance of the system. Zero order feedback loop absorption loop delay, NRZ feedback pulse waveform to suppress clock jitter, capacitive tuning array to calibrate integral constant fluctuation, and DWA algorithm to improve multi-bit quantizer mismatch are adopted. Finally, on the basis of the structure of the third-order continuous time Sigma-Delta modulator, which has been verified by the behavior level, the circuit analysis and design are developed. Using SMIC 0.18m 1P6M process, the SFDR is 98.4 dBU SNR 81.1 dB SNDR and the effective bit is 11.2 bits under the condition that the power supply voltage 1.8 V 10 MHz signal bandwidth OSR is 16. The simulation results show that the SFDR is 98.4 dBU SNR is 81.1 dBN SNDR is 80.9 dB, and the effective bit is 11.2 bits.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761

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