嵌入广义折叠技术的集成电路测试数据压缩方案

发布时间：2018-05-20 16:22

本文选题：内建自测试 + 折叠集　；参考：《计算机辅助设计与图形学学报》2017年08期

【摘要】：针对芯片测试过程中自动测试设备需要传输大量测试数据到被测芯片,浪费了大量的测试数据传输时间的问题,提出一种广义折叠技术的集成电路测试数据压缩方案.首先构建有向图,将完全测试集映射到有向图中;其次查找有向图中最长路径,将完全测试集分割成若干个广义折叠集;最后存储广义折叠集的种子和广义折叠距离.另外,提出了广义折叠集的解压结构.理论上可以将整个测试集的存储转化成若干个广义折叠种子和广义折叠距离的存储.对部分ISCAS89标准电路中规模较大的时序电路进行实验的结果表明,在同样实验环境下,该方案在压缩效果方面优于Golomb码、FDR码、EFDR码和折叠集等成熟的压缩方法.
[Abstract]:In order to solve the problem that the automatic test equipment needs to transmit a large amount of test data to the chip and waste a lot of test data transmission time in the process of chip testing, a scheme of integrated circuit test data compression based on generalized folding technique is proposed. First, the directed graph is constructed to map the complete test set to the directed graph; secondly, the longest path in the directed graph is found, and the complete test set is divided into several generalized folding sets; finally, the seed and the generalized folding distance of the generalized folding set are stored. In addition, the decompression structure of generalized folded sets is proposed. In theory, the storage of the whole test set can be transformed into several generalized folding seeds and the storage of generalized folding distance. The experimental results of some large-scale sequential circuits in ISCAS89 standard circuits show that under the same experimental environment, this scheme is superior to the mature compression methods such as Golomb code / EFDR code and folding set in compression effect.
【作者单位】：安庆师范大学计算机与信息学院;
【基金】：国家自然科学基金(61640421,61306046) 安徽省学术带头人后备人选(gxbj ZD2016075,2015H053) 安徽省高校自然科学研究重点项目(KJ2016A427)
【分类号】：TN407

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