高k栅介质CMOS集成电路老化模型研究

发布时间：2018-05-20 17:32

本文选题：可靠性 + 电路老化　；参考：《合肥工业大学》2015年硕士论文

【摘要】：随着集成电路技术的飞速发展,其工艺尺寸也越来越小,使得集成电路的集成度与功能得到大幅度的提高,然而这也为电路可靠性带来更大挑战。作为影响电路可靠性的一个重要因素,电路老化,研究者们一直对其保持着高度关注。目前关于老化的研究主要包含老化效应模型研究与老化效应的优化两个方面,并且集中于硅基MOS管与集成电路中。当集成电路工艺尺寸缩小到45nm及以下时,为了缓解愈加严重的漏电流现象,高k材料开始引进。本文主要是研究在高k栅介质晶体管中,关于电路老化效应的建模问题。高k材料的引进,使得发生在NMOS管上的PBTI与TDDB效应越来越显著。本文针对高k材料NMOS管,通过建立电路固有时延与老化后时延的联系,提出一种综合PBTI与TDDB效应的老化混合时延模型。运用Hspice软件在45nm、32nm、22nm以及16nm工艺库下的实验结果表明,提出模型的分析数据与实际值最大误差不超过2.5%,平均误差大约为1.5%,验证了该模型的准确性。并且通过反相器链对比试验,同时考虑这两种老化效应的电路时延,比这两种效应分别对时延影响单纯叠加的结果更加精确,因此本文为高k材料晶体管组成的电路老化时延提供了一种较为简便的预测算法。在高k材料晶体管中,基于新提出的电荷俘获释放机制,通过线性分析和数据拟合,研究建立基础逻辑门在PBTI效应下新的老化时延模型。通过实验对比,新提出的模型与Hspice仿真结果在8到12年的预测时间内,平均误差处于2%至4.5%之间,验证了模型的正确性。并且在基于不同关键路径的时序余量设置实验中,当时间指数n取值分别为0.16与0.25时,在同样保证电路可靠性的前提下,与之前的老化时延模型比较,本文模型所设置的时序余量有显著减小,为时序余量的设置提供更优的参考。
[Abstract]:With the rapid development of integrated circuit technology, its process size is becoming smaller and smaller, which greatly improves the integration and function of integrated circuits. However, it also brings greater challenges to the reliability of circuits. As an important factor affecting the reliability of circuits, researchers have been paying close attention to the aging of circuits. At present, the research on aging mainly includes two aspects: aging effect model research and aging effect optimization, and it is concentrated in silicon based MOS transistors and integrated circuits. When the IC process size is reduced to 45nm and below, in order to alleviate the increasingly serious leakage current phenomenon, high-k materials are introduced. In this paper, we study the modeling of circuit aging effect in high k gate transistors. With the introduction of high k materials, the PBTI and TDDB effects on NMOS tubes become more and more obvious. In this paper, a hybrid time-delay model based on PBTI and TDDB effects is proposed for high k NMOS transistors by establishing the relationship between the inherent delay and the aging delay. The experimental results using Hspice software at 45nm ~ 32nm ~ 22 nm and 16nm process library show that the maximum error between the analysis data and the actual value of the proposed model is not more than 2.5, and the average error is about 1.5. The accuracy of the model is verified. And the circuit delay considering the two aging effects is more accurate than the results of the simple superposition of the two effects on the delay through the contrasting experiment of the inverter chain at the same time. Therefore, this paper provides a simple prediction algorithm for the aging delay of high k transistors. Based on the newly proposed charge capture and release mechanism in high k transistors, a new aging delay model of the basic logic gates under the PBTI effect is studied by linear analysis and data fitting. The experimental results show that the average error between the proposed model and the Hspice simulation results is between 2% and 4.5% in 8 to 12 years, which verifies the correctness of the model. In the experiment of time series allowance setting based on different critical paths, when the time exponent n is 0.16 and 0.25 respectively, the reliability of the circuit is also guaranteed and compared with the previous aging delay model. The time series allowance set by this model is significantly reduced, which provides a better reference for the setting of time series allowance.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN432

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