基于自适应电源调整的FPGA抗退化方法研究

发布时间：2018-05-20 19:15

本文选题：FPGA + NBTI效应　；参考：《哈尔滨工业大学》2017年硕士论文

【摘要】：FPGA(Field Programmable Gate Array)现场可编辑逻辑门阵列,是当今硬件设计中应用十分广泛的新型高性能逻辑器件。FPGA具有功能强大、开发周期短、可反复编程修改、开发工具智能化等优点。但是随着超大规模集成电路加工工艺的提升日益困难,FPGA性能已经逐渐达到其物理极限。同时,FPGA器件面临的可靠性问题也日益严重。在众多可靠性问题中,负偏压温度不稳定性效应(Negative Bias Temperature Instability,NBTI)是FPGA器件失效的首要原因,NBTI效应造成的性能退化使FPGA随着时间推移产生更多的信号延迟从而导致信号在逻辑门之间的传输时间逐渐延长,并最终导致电路出现时序违规问题。本文首先分析了FPGA内部结构,以及NBTI效应造成FPGA工作速率退化的本质原因。以此为基础,本文设计了FPGA器件加速退化试验平台,利用基于失效物理的方法,对FPGA进行加速退化试验,获取FPGA在不同应力组合情况下的退化情况。本文随后研究了电源电压对FPGA路径延迟的影响,并利用HSPICE软件仿真分析了电源电压对FPGA内部查找表单元结构和互连结构延迟时间的影响。此外,本文还提出基于环形振荡器的路径延迟测量方法,通过在FPGA中进行真实硬件实验验证了电源电压升高对于路径延迟退化的抑制作用。以此研究为基础,本文提出了基于自适应电源调整的FPGA抗退化方法基本框架,并设计退化传感器对FPGA路径延迟退化情况进行实时监测,同时根据退化情况对电源电压进行动态调整,已达到保证电路工作性能,并且减小电路功率消耗的目的。最后,本文搭建了基于自适应电源调整方法完整的实现平台和验证平台。通过该平台证明了该方法可以有效消除FPGA退化的影响,具有鲁棒性强、响应速度快的特点。并且以FFT运算核作为试验对象,将该方法与传统方法保留时序余量法进行了功耗和性能对比。在工作频率相同的情况下,该方法最大可将功耗降低57.98%,在功耗相同的情况下,该方法最高可将电路最大工作频率提高14.78%。
[Abstract]:FPGA(Field Programmable Gate Array) field editable logic gate array is a new type of high performance logic device which is widely used in hardware design nowadays. It has many advantages such as powerful function, short development period, reprogramming modification, intelligent development tool and so on. However, with the improvement of VLSI processing technology, FPGA performance has gradually reached its physical limit. At the same time, the reliability of FPGA devices is becoming more and more serious. Among the many reliability problems, The negative bias temperature instability effect (NBTI) is the primary reason for the failure of FPGA devices. The performance degradation caused by the NBTI effect causes the FPGA to produce more signal delays over time, which leads to the gradual extension of signal transmission time between logic gates. And eventually lead to circuit timing violations. In this paper, we first analyze the internal structure of FPGA and the essential cause of the degradation of FPGA working rate caused by NBTI effect. Based on this, an accelerated degradation test platform for FPGA devices is designed. Using the method of failure physics, the accelerated degradation test of FPGA is carried out, and the degradation of FPGA under different stress combinations is obtained. Then, the influence of power supply voltage on FPGA path delay is studied, and the influence of power supply voltage on FPGA internal lookup form element structure and interconnect structure delay time is simulated by HSPICE software. In addition, a path delay measurement method based on ring oscillator is proposed. The effect of voltage rise on path delay degradation is verified by a real hardware experiment in FPGA. On the basis of this research, this paper presents the basic framework of FPGA anti-degradation method based on adaptive power supply adjustment, and designs a degradation sensor to monitor the degradation of FPGA path delay in real time. At the same time, the power supply voltage is dynamically adjusted according to the degradation situation, which can ensure the circuit performance and reduce the power consumption of the circuit. Finally, a complete implementation platform and verification platform based on adaptive power adjustment method are built. It is proved by the platform that this method can effectively eliminate the influence of FPGA degradation and has the characteristics of strong robustness and fast response speed. Taking the FFT operation kernel as the experimental object, the power consumption and performance of the proposed method are compared with that of the traditional method. In the case of the same operating frequency, the maximum power consumption can be reduced by 57.98. In the case of the same power consumption, the maximum operating frequency of the circuit can be increased by 14.78.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791

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