基于OC8051芯片处理器的3D IC布局布线设计

发布时间：2018-05-20 20:16

本文选题：三维集成电路 + 硅通孔　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着集成电路技术的发展,在单芯片上可集成的电路规模及复杂度不断增加。采用传统的平面工艺,过长互连线产生的延迟严重制约了系统性能的提高,三维集成电路已经成为下一代高性能集成电路的首选方案。为了解决现有EDA设计工具不能满足三维集成电路设计需求的问题,本文重点研究多个芯片通过三维互连通孔的方法,来进行三维集成电路设计时的自动布局布线的方法和流程。在分析三维集成电路结构的特点的基础上,重点对F2F及硅通孔这两种通孔结构的三维集成电路自动布局布线方法进行研究。首先在EDA软件环境下建立了F2F和硅通孔TSV的模型,通过sed语言处理输入输出约束文件将凸点变为可识别的金属端口解决了硅通孔和F2F互连通孔在二维EDA软件中识别和应用问题。其次,以OC8051芯片处理器代码为例,完成了三维集成电路布局布线流程的设计。在设计过程中,首先对OC8051芯片处理器代码进行了分割,将其分为逻辑功能计算部分(核区)及存储部分(静态随机存储器)两个芯片。通过引入了Wide I/O的概念对OC8051芯片处理器的数据部分与电源部分两个需要进行三维互连的部分做了布局规划,并对三维互连端口进行了隔离处理。使用二维EDA软件SOC Encounter对三维芯片的两个裸片分别进行布图布局、时钟树综合、布线等版图的设计,最终通过Virtuoso将硅通孔的版图结构合并到版图中。通过比对二维物理设计,三维物理设计使OC8051芯片处理器的时序违例降低了60%以上,证明了流程的正确性。本论文建立了三维集成电路自动布局布线的基本流程,为全面实现三维集成电路的设计奠定了后端流程基础。
[Abstract]:With the development of integrated circuit technology, the scale and complexity of integrated circuits on single chip are increasing. The system performance is greatly restricted by the delay caused by the long interconnect in the traditional plane process. The 3D integrated circuit has become the first choice of the next generation high performance integrated circuit. In order to solve the problem that the existing EDA design tools can not meet the needs of 3D IC design, this paper focuses on the method and flow of automatic layout and routing for 3D IC design by means of 3D interconnect through holes. On the basis of analyzing the characteristics of 3D integrated circuit structure, the automatic layout and routing method of F2F and silicon through hole are studied. Firstly, the model of F2F and via TSV is established under the EDA software environment. By processing the input and output constraint files in sed language, the convex point is turned into an identifiable metal port, which solves the problem of identifying and applying the silicon through hole and the F2F interconnection through hole in the two-dimensional EDA software. Secondly, taking the OC8051 chip processor code as an example, the layout and routing process of 3D integrated circuit is designed. In the design process, the processor code of OC8051 chip is divided into two chips: logical function calculation (core area) and memory (static random access memory). By introducing the concept of Wide I / O, the layout planning of the data part and the power part of the OC8051 chip processor are made, and the three dimensional interconnection ports are isolated. Two dimensional EDA software SOC Encounter is used to design the layout of the two bare chips of the 3D chip. Finally, the layout structure of the silicon through hole is incorporated into the layout through Virtuoso, including the layout, clock tree synthesis, wiring and so on. Compared with two-dimensional physical design, 3D physical design can reduce the timing violation of OC8051 chip processor by more than 60%, which proves the correctness of the flow chart. In this paper, the basic flow of 3D IC automatic layout and routing is established, which lays a foundation for the design of 3D IC.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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