低延迟自组织网的网络层FPGA设计与实现

发布时间：2018-05-23 20:11

本文选题：自组织网 + 低延迟　；参考：《电子科技大学》2015年硕士论文

【摘要】：不同于传统有中心节点的基站-移动终端模式的无线网络,无线自组织网是一种由若干个对等设备自由组成的无线网络。由于其具有网络结构灵活、可独立组网、抗毁性强等优势,无线自组织网已成为了无线通信技术发展的重要方向之一。无线自组织网通常采用CSMA/CA或TDMA的接入方式,其端到端传输时延较大,不适用于如军事通信等对时延要求较高的场合。为解决自组织网中通信节点传输时延较大的问题,本文在以太网接口和物理层链路的基础上,设计并在FPGA上实现了一种竞争和时分多址相结合的接入和组网方式,并实现了节点间的高精度全局时间同步。全文的主要工作如下:首先,讨论了现有的自组织网接入方式以及常见的时间同步算法,并根据机载自组织网的时间同步及数据传输应用场景,以及物理层链路和硬件系统的约束,提出了明确的低延迟自组织网的网络层设计指标。其次,根据设计指标,分为广播通道、数据通道、收发切换三个大模块设计了低延迟自组织网的网络层方案,分别用于实现节点入退网及高精度时间同步、用户IP化业务数据传输及TDD信道接入控制三大功能,并给出了一种在竞争接入模式和时分多址接入模式之间灵活切换的流程。随后,分模块详细讨论了广播通道、数据通道和收发切换三大模块的FPGA实现细节,包括各大模块的总体结构框图、各子模块的状态转移、组帧与解帧的流程,以及竞争和时分多址接入模式的收发切换控制,并给出了一种通过以太网接口的UDP配置通道进行链路管理的方法。最后,本文对网络层连同物理层一起的全链路,分为双节点AD/DA回环和多节点无线传输两个场景进行了详细的测试。结果表明,实现后的网络层配合物理层链路可以在100km范围内实现最小4.5ms的端到端延迟,提供最大约6.4Mbps的单向传输带宽,可支持各种类型的以太网数据包,并实现4ns的同步精度。本文的研究内容给出了一种基于FPGA的低延迟自组织网的解决方案,具有较强的可扩展性,为自组织网的低延迟应用提供了参考方案
[Abstract]:Unlike the traditional base-mobile terminal wireless network with central nodes, the wireless ad hoc network is a wireless network composed of several peer-to-peer devices. Due to the advantages of flexible network structure, independent networking and strong survivability, wireless ad hoc networks have become one of the important development directions of wireless communication technology. Wireless ad hoc networks usually use CSMA/CA or TDMA access mode, their end-to-end transmission delay is large, so it is not suitable for military communications. In order to solve the problem of long transmission delay of communication nodes in ad hoc networks, based on Ethernet interface and physical layer link, this paper designs and implements a competitive and time-division multiple access (TDMA) access and networking mode on FPGA. The high precision global time synchronization between nodes is realized. The main work of this paper is as follows: firstly, the existing access methods and the common time synchronization algorithms are discussed, and according to the time synchronization and data transmission scenarios of the airborne ad hoc network, As well as the constraints of physical layer link and hardware system, a clear network layer design index of low delay ad hoc network is proposed. Secondly, according to the design index, it is divided into three modules: broadcast channel, data channel and transceiver switch. The network layer scheme of low delay ad hoc network is designed, which is used to realize node entry and exit network and high precision time synchronization, respectively. User IP traffic data transmission and TDD channel access control are three main functions, and a flexible switching process between competing access mode and time division multiple access mode is given. Then, the FPGA implementation details of broadcast channel, data channel and transceiver switch are discussed in detail, including the overall structure block diagram of each module, the state transition of each sub-module, the process of framing and unframing. And the transceiver switching control of competition and time division multiple access (TDMA) mode, and a method of link management through the UDP configuration channel of Ethernet interface is presented. Finally, the whole link of network layer and physical layer is divided into two scenarios: two-node AD/DA loop and multi-node wireless transmission. The results show that the realized network layer with physical layer link can realize the end-to-end delay of the minimum 4.5ms in the range of 100km, provide the maximum one-way transmission bandwidth of about 6.4Mbps, support all kinds of Ethernet packets, and realize the synchronization accuracy of 4ns. In this paper, a solution of low delay ad hoc network based on FPGA is presented, which has strong extensibility and provides a reference scheme for low delay application of ad hoc network.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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