一种钳位电路的ESD保护研究与实现

发布时间：2018-05-26 05:38

本文选题：静电放电(ESD) + 钳位电路(Clamp　；参考：《东南大学》2015年硕士论文

【摘要】：在现代集成电路工业中调查显示,大约有37%的IC(Integrated Circuit)芯片失效与ESD/EOS (Electro-StaticDischarge/Electricity Over Stress)有关,随着电路的集成度增加、栅氧厚度减薄、更高的工作频率,电子元器件技术的发展,静电对元器件的影响也越来越敏感。随着IC芯片尺寸的持续缩小,ESD问题表现得也更加突出,ESD已经成为高集成度IC芯片中需要重视并着力解决的一个重要问题。因此,为了获得性能更好,可靠性更高的IC芯片,对ESD开展深入的研究并且找到解决方法十分必要。产品研发是以成本最小化、利润的最大化为基本出发点,所以ESD的设计通常都是采用简单的GGNMOS的保护,并没有考虑用电路级保护或者是二级保护。原因在于电路级保护或是二级保护耗费面积且增加成本,因此ESD的问题很难得到有效的解决。随着市场的变化和应用要求的提高,在不增加成本的条件下解决ESD问题,面临越来越大的挑战。论文选择IC产品高效实用ESD设计研究,有比较重要的现实意义。论文以ESD保护器件作为研究对象,从静电的基本模型出发,阐述了各种模型的定义与标准。其中以工业中最常用的人体模型(HBM-Human Body Model)为主要的测量ESD能力的标准。本论文给出了改进了实际产品中钳位电路的ESD保护方案,即由原来的GGNMOS (Gate Gnd NMOS)保护方案改进为GRNMOS (Gate Resistance NMOS)保护方案,通过分析钳位电路的特点及工作原理,钳位控制电路开启前泄放静电电流,通过降低ESD保护器件的触发电压可以保护钳位电路的钳位管,通过实验找到合适的触发电压Vtr。最终产品由原来HBM测试不到500V,通过使用GRNMOS保护方案使其ESD能力提高到4000V。实验结果表明：通过TLP测试及HBM(4KV)测试模式下,改进设计的ESD性能明显提升并均能达到目标要求,而且在成本方面并没有增加额外的费用
[Abstract]:Investigation in the modern integrated circuit industry shows that about 37% of the IC(Integrated circuit chip failures are related to the ESD/EOS Electro-Static charge / electricity Over chips. With the increasing integration of the circuit, the thickness of the gate oxygen is thinned, the working frequency is higher, and the technology of electronic components is developing. The influence of static electricity on components is becoming more and more sensitive. With the continuous reduction of IC chip size, the ESD problem has become more prominent. ESD has become an important problem that needs to be paid attention to and solved in high integrated IC chips. Therefore, in order to obtain IC chips with better performance and higher reliability, it is necessary to do in-depth research on ESD and find solutions. Product development is based on cost minimization and profit maximization, so ESD design usually adopts simple GGNMOS protection, and does not consider circuit level protection or secondary protection. The reason is that circuit level protection or secondary protection consumes area and increases cost, so the problem of ESD is difficult to be solved effectively. With the change of the market and the improvement of the application requirements, it is facing more and more challenges to solve the ESD problem without increasing the cost. The thesis chooses the IC product high efficiency practical ESD design research, has the more important practical significance. In this paper, ESD protection device is taken as the research object, and the definition and standard of various models are expounded from the basic model of static electricity. HBM-Human Body Model, the most commonly used human model in industry, is the main standard for measuring ESD capability. In this paper, the ESD protection scheme of the clamp circuit in the actual product is presented, that is, the original GGNMOS gate Gnd NMOS protection scheme is improved to the GRNMOS gate Resistance NMOS) protection scheme. The characteristics and working principle of the clamp circuit are analyzed. The clamp control circuit releases the electrostatic current before opening, and the clamp tube of the clamp circuit can be protected by reducing the trigger voltage of the ESD protection device. The final product was tested by less than 500V from the original HBM, and its ESD capability was increased to 4000V by using the GRNMOS protection scheme. The experimental results show that under the TLP test and HBM4KV) test mode, the ESD performance of the improved design is obviously improved and can reach the target requirements, and no additional cost is added in the cost.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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