基于扫描设计的集成电路可测试性设计研究

发布时间：2018-05-26 08:40

本文选题：SOC测试 + 扫描链平衡　；参考：《贵州大学》2016年硕士论文

【摘要】：如今,IP的复用技术在芯片上得到了广泛的使用,通过芯片复用的方法,芯片的体积,功耗,性能等一些指标都有了相对的改善。但是面对着芯片的复杂程度越来越多,传统的测试手段早已不能满足芯片的发展速度,芯片的测试难度已经引起了相关学者的关注,而对于SOC的测试成本的主要因素——测试时间的优化研究成为众多学者的研究方向,利用何种手段可以更好的降低测试时间,降低测试所带来的高成本成为待解决的难题。通过使用可测试性技术,不仅可以增加芯片电路的可控制性、可观测性,同时也将芯片的测试难度大大降低。针对芯片的可测试性设计来说,最大的问题就是测试时间,针对测试时间优化。本文主要内容:首先,扫描链的研究设计,针对不同情况的测试向量单元进行相应的扫描链设计优化,主要方法有重排序法和Huffman算法。其次,并且讨论了多扫描链的测试调度问题,主要算法包括BFD算法、MAV算法、TAD算法。并对着三种算法进行了相应的扫描链设计安排比较。再次,本文同时也讨论了故障模型的测试算法,在不同的故障下,比较了不同的测试算法的应用领域。最后,BIST模块的建立测试,主要是从测试向量生成器、读写地址生成器、特征值向量比较器等进行了RTL级的相关结构设计,并通过Verdi Fundamental Training工具进行仿真,验证了整个设计的正确性。
[Abstract]:Nowadays, the reuse technology of IP has been widely used in the chip. Through the method of chip reuse, the volume, power consumption and performance of the chip have been relatively improved. However, in the face of more and more complex chips, the traditional testing methods have not been able to meet the speed of the development of chips, the difficulty of chip testing has attracted the attention of relevant scholars. However, the research on the optimization of test time, which is the main factor of SOC test cost, has become the research direction of many scholars. What means can be used to better reduce the test time and reduce the high cost of testing becomes a difficult problem to be solved. By using testability technology, not only the controllability and observability of chip circuits can be increased, but also the difficulty of chip testing can be greatly reduced. For the testability design of the chip, the biggest problem is the test time, aiming at the test time optimization. The main contents of this paper are as follows: firstly, the research and design of scan chain, and the corresponding scan chain design optimization for different test vector units are carried out. The main methods are reordering method and Huffman algorithm. Secondly, the test scheduling problem of multi-scan chain is discussed. The main algorithms include BFD algorithm and MAV algorithm. The corresponding scan chain design arrangements are compared among the three algorithms. Thirdly, this paper also discusses the test algorithms of fault models, and compares the application fields of different test algorithms under different faults. Finally, the establishment and test of the BIST module is mainly carried out from the test vector generator, the read-write address generator, the eigenvalue vector comparator and so on, and the related structure design of RTL level is carried out, and the simulation is carried out through the Verdi Fundamental Training tool. The correctness of the whole design is verified.
【学位授予单位】：贵州大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN407

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