高速SerDes中时钟数据恢复电路的设计研究

发布时间：2018-05-27 19:06

本文选题：时钟数据恢复 + 高速串行接口　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：随着集成电路行业的迅速发展,以及信息流量需求的不断增大,目前高性能芯片的数据计算和处理速度已经很快,而芯片之间的数据传输速率相对落后成为了制约芯片性能的最大瓶颈。传统的并行传输技术因其需要过多的管脚数目、各数据位之间的传输延时不匹配和需要同步时钟等原因而逐渐被淘汰,取而代之的是原本应用于光纤通信的串行传输技术——SerDes(Serializer/Deserializer)。时钟数据恢复(CDR)电路是整个Ser Des系统的核心,也是制约着其性能的关键所在,它的主要功能是从接收到的含有较大串扰和抖动的数据中恢复出时钟,并利用这个时钟对该数据进行采样,从而得到正确的数据。本文基于65 nm CMOS工艺,完成了对高速SerDes中的关键模块CDR的研究和设计。本文首先从MATLAB建模出发,运用数学模型深入研究了CDR的工作原理,然后在模型的指导下,完成了相应的电路设计和版图设计。本文设计的CDR采用基于相位插值(PI)的双环结构实现,其中一个环路为锁相环(PLL),另一个环路为延迟锁相环(DLL)。其中DLL由相位插值电路、高速采样电路、数据分接电路、边沿检测电路和二阶数字环路滤波器等组成。支持1.25 Gb/s~6.25 Gb/s的宽范围工作速率,支持半速、全速和倍速三种工作模式,降低了锁相环的设计难度,且具有带宽可调和一定频差容忍等特点,其中相位插值电路采用7 bit的结构。为了提高有频差时的锁定速度,本文还创新性地在二阶数字环路滤波器中增加了快速锁定算法,使其在频差为1000 ppm时锁定速度可以提高一倍,能够满足突发性数据传输的要求。仿真结果表明,在工作速率为6.25 Gb/s时,该CDR抖动传输带宽为2 MHz~7.5 MHz可调,最大频差容忍为±1800 ppm,在频差为1800 ppm时恢复出的数据眼图宽度大于0.89 UI,功耗小于16.4 mW。其中相位插值电路的DNL为2.8o,INL为7.2o。仿真结果满足系统设计指标。
[Abstract]:With the rapid development of integrated circuit industry and the increasing demand of information flow, the data calculation and processing speed of high performance chip has been very fast. The relative lag of data transmission rate between chips has become the biggest bottleneck of chip performance. The traditional parallel transmission technology is gradually eliminated because of the excessive number of pins, the mismatch of transmission delay between different data bits and the need of synchronous clock. Instead, SerDesSerializer / Deserializerer, the serial transmission technology originally used in optical fiber communication, is replaced. The clock data recovery circuit is the core of the whole Ser Des system and the key to its performance. Its main function is to recover the clock from the received data with large crosstalk and jitter. This clock is used to sample the data to get the correct data. Based on 65 nm CMOS process, the research and design of CDR, a key module in high speed SerDes, is completed in this paper. Based on the MATLAB modeling, the working principle of CDR is studied deeply by using the mathematical model, and then the corresponding circuit design and layout design are completed under the guidance of the model. The CDR designed in this paper is based on phase interpolation (Pi) double loop structure. One loop is phase locked loop (PLL) and the other is delay phase locked loop (DLL). DLL consists of phase interpolation circuit, high speed sampling circuit, data demultiplexing circuit, edge detection circuit and second order digital loop filter. It supports three working modes of half speed, full speed and double speed, which reduces the design difficulty of phase-locked loop, and has the characteristics that bandwidth can be reconciled with a certain frequency difference tolerance. Among them, the phase interpolation circuit adopts a 7 bit structure. In order to improve the locking speed with frequency difference, this paper also creatively adds a fast locking algorithm to the second-order digital loop filter, which can double the locking speed when the frequency difference is 1000 ppm, and can meet the requirements of sudden data transmission. The simulation results show that when the operating rate is 6.25 Gb/s, the CDR jitter transmission bandwidth is 2 MHz~7.5 MHz adjustable, the maximum frequency difference tolerance is 卤1800 ppm, and the recovery data eye width is greater than 0.89 UIwhen the frequency difference is 1800 ppm, and the power consumption is less than 16.4 MW. The DNL of the phase interpolation circuit is 2.8oNL and 7.2o. The simulation results meet the system design criteria.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN432

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