基于FPGA的新型全数字锁相环的设计与实现

发布时间：2018-05-28 15:53

本文选题：全数字锁相环 + 自适应控制　；参考：《电子科技大学》2015年硕士论文

【摘要】：锁相环(PLL)是一个闭环负反馈控制系统,能够对输入信号的相位和频率进行有效地跟踪。在通信、自动化以及电力系统等领域,锁相环得到了广泛的应用。由于其优良的性能,已经成为各类电子系统中重要的、不可缺少的基本元器件。与模拟锁相环相比,全数字锁相环(ADPLL)具有参数稳定、抗干扰能力强以及易于集成等特点。另外,ADPLL解决了模拟锁相环中存在的压控振荡器非线性、鉴相器精度不高、各个部件易于饱和、以及高阶系统不稳定等难题,因此,ADPLL得到了越来越多的应用。到目前为止,全数字锁相环的结构和控制方式已经是多种多样了,而锁定时间短、同步误差小、跟踪频率范围广以及抗干扰能力强等是衡量一个锁相环系统优良的标准。针对传统全数字锁相环设计中因控制参数固定而导致频率跟踪范围窄的问题,本文设计了一种采用自适应控制与PI控制相结合的方法实现的新型全数字锁相环,该锁相环可以使环路的带宽随输入信号频率的改变而自动改变。另外,针对传统数字锁相环锁定时间与抗干扰能力之间无法协调控制的问题,本文通过所设计的自适应控制器根据相差的大小将环路捕捉过程分为快捕区、过渡区以及慢捕区,使控制参数随这三个过程自动调节,有效解决了环路锁定时间与抗噪声性能之间矛盾的问题。另外,当输入信号频率发生突变后,传统的全数字锁相环会重新开始较长的锁定过程,本文针对这个问题,设计了一种频率控制字预置电路,该电路可以使环路在一个周期实现对信号的锁定,大大减小了锁定时间。本文在研究环路各模块以及分析整体数学模型的基础上,最终,在Quartus II软件环境下,采用自顶向下的模块化设计思路完成了整个系统电路的设计,并进行了编译、综合和仿真,最后在可编程器件上完成硬件实测。软件功能仿真与硬件实测结果表明:所设计的锁相环的带宽随输入信号的频率改变而改变,同时相比传统PI控制锁相环,锁定时间较短且同步误差较小,可用于有快速同步需求的场合。当系统时钟为50MHz时,在环路分频系数为N=64的情况下,环路的锁定时间最慢在8个输入信号周期,最快可在一个周期完成锁定,环路稳定时的同步误差为?160ns,频率跟踪范围为40Hz~390KHz,且该锁相环电路具有结构简单、易于集成的特点。
[Abstract]:PLL is a closed loop negative feedback control system, which can effectively track the phase and frequency of the input signal. In the fields of communication, automation and power system, PLL has been widely used. Because of its excellent performance, it has become an important and indispensable basic component in all kinds of electronic systems. Compared with analog PLL, ADPLL has the advantages of stable parameters, strong anti-jamming ability and easy integration. In addition, ADPLL solves the problems of nonlinear voltage controlled oscillator in analog PLL, low precision of phase discriminator, easy saturation of each component, and instability of high order system, so ADPLL has been applied more and more widely. Up to now, the structure and control methods of all-digital phase-locked loop have been varied, but short locking time, small synchronization error, wide tracking frequency range and strong anti-jamming ability are the good standards for a phase-locked loop system. In order to solve the problem that the frequency tracking range is narrow due to the fixed control parameters in the design of traditional all-digital phase-locked loop, a novel all-digital phase-locked loop is designed by combining adaptive control with Pi control in this paper. The PLL can automatically change the bandwidth of the loop with the change of the input signal frequency. In addition, aiming at the problem that the locking time of traditional digital phase-locked loop can not be coordinated with the anti-jamming ability, the loop capture process is divided into fast capture area, transition region and slow capture area by the designed adaptive controller according to the size of the phase difference. The control parameters are automatically adjusted with these three processes, and the contradiction between loop locking time and anti-noise performance is effectively solved. In addition, when the input signal frequency changes, the traditional all-digital phase-locked loop will start the longer locking process again. In this paper, a frequency control word preset circuit is designed to solve this problem. The circuit enables the loop to lock the signal in one cycle, greatly reducing the locking time. On the basis of studying each module of loop and analyzing the whole mathematical model, finally, under the environment of Quartus II software, the whole system circuit is designed by using top-down modular design idea, and the whole system circuit is compiled, synthesized and simulated. Finally, the hardware measurement is completed on the programmable device. The results of software function simulation and hardware measurement show that the bandwidth of the designed PLL changes with the frequency of the input signal, and the locking time is shorter and the synchronization error is smaller than that of the traditional Pi PLL. Can be used for the need for rapid synchronization. When the system clock is 50MHz, the locking time of the loop is the slowest in 8 input signal cycles when the loop frequency division coefficient is NB64, and the lockout can be completed in one cycle as soon as possible. When the loop is stabilized, the synchronization error is 160 ns and the frequency tracking range is 40 Hz ~ 390kHz. The PLL circuit has the characteristics of simple structure and easy integration.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP273;TN791

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