高速网络数据包解析器设计与FPGA实现

发布时间：2018-05-29 01:10

本文选题：数据包解析器 + CAM　；参考：《电子科技大学》2015年硕士论文

【摘要】：近十年来网络技术高速发展,给大家带来便利的同时,越来越多设备对路由器和交换机的性能以及可配置性提出了迫切需求。为了建立高效、稳定和安全的网络系统,网络设备生产商们更加关注于其设备的通用性和扩展性,而这些无一例外的体现在了对数据包进行解析,识别包头和提取数据上,以支持对数据包的分类和安全功能。过去对于数据包的解析相对比较简单,然而随着MPLS(Multi-Protocol Label Switching)和802.1Q等夹层协议的加入,使得高速的解析数据包越发的困难。通常在没有夹层协议的情况下,数据包解析器的吞吐率可达到10-100Gbps。然而,在夹层协议下,数据包解析器的吞吐率却急剧下降。因此在高速路由器或交换机中,数据包的解析就成了潜在的瓶颈。为了解决上述问题,要求更加高效的实现解决方案。本文将围绕灵活的高速网络数据包解析器的架构设计展开研究。首先,本文研究并归纳整理了近几年国内外对高速网络数据包解析器架构设计的方法,对比分析了各种高速网络数据包解析器架构设计的优缺点。其次,本文提出了一种新颖的灵活数据包解析器架构。通过采用流水线技术,CAM(Content Addressable Memory)和LUT(Look Up Table)的联合存储查询结构,该架构能够自适应新的数据包头(包含夹层协议和隧道以太网帧等)。另外,本文还提出了一种离线映射算法,通过离线映射,该架构能够在一个流水级中一次性解析多个协议组合,并拥有非常高的灵活性和吞吐率。最后,本文选择Altera公司的FPGA开发平台,对该架构进行了实现。根据实际网络中存在的以太网帧,对数据包解析器架构进行了性能测试,并给出了硬件资源,工作时钟频率等信息。相对已有的数据包解析器架构,本文提出的数据包解析器架构硬件资源上有一定的消耗,但灵活性和吞吐率却有了更高的提升,且增加了与处理器进行交互的接口和中断系统。传统的并行多级流水架构,对于固定的以太网帧,解析速率可达100Gbps,但是灵活性较低。而灵活性最高的袋鼠系统架构,其四路并行解析核下的吞吐率为40Gbps,难以适应更加高速的网络。而本文提出的数据包解析器架构能够在工作频率411MHz下达到105Gbps的解析速率,实现了数据包解析器的高灵活性和高吞吐率。
[Abstract]:With the rapid development of network technology in the past ten years, more and more devices have put forward an urgent need for the performance and configurability of routers and switches. In order to build efficient, stable and secure network systems, network equipment manufacturers pay more attention to the versatility and expansibility of their devices, which are reflected in the parsing of data packets, the identification of packet heads and the extraction of data. To support packet classification and security. In the past, the parsing of data packets was relatively simple, but with the addition of MPLS(Multi-Protocol Label switching and 802.1Q protocols, it became more and more difficult to parse packets at high speed. In the absence of a mezzanine protocol, the throughput of the packet resolver can reach 10-100 Gbps. However, in the interlayer protocol, the throughput of packet parser drops sharply. Therefore, in high-speed routers or switches, packet parsing becomes a potential bottleneck. In order to solve the above problem, we need to implement the solution more efficiently. This paper focuses on the architecture design of a flexible high-speed packet parser. Firstly, this paper studies and summarizes the architecture design methods of high-speed network packet parser in recent years, and compares and analyzes the advantages and disadvantages of various high-speed network packet parser architecture design. Secondly, a novel flexible packet parser architecture is proposed. By adopting the combined storage and query structure of the pipeline technology, including the CAM content Addressable memory and the LUT(Look up Table, this architecture can adapt to the new data packet header (including the mezzanine protocol and the tunneling Ethernet frame etc.). In addition, an off-line mapping algorithm is proposed. By off-line mapping, the architecture can resolve multiple protocols in a pipeline level at one time, and has high flexibility and throughput. Finally, this paper chooses the FPGA development platform of Altera Company and implements the architecture. According to the Ethernet frame in the actual network, the performance of the packet parser architecture is tested, and the information of hardware resources, working clock frequency and other information are given. Compared with the existing packet parser architecture, the hardware resources of the proposed packet parser architecture are consumed to a certain extent, but the flexibility and throughput are improved, and the interface and interrupt system are added to interact with the processor. Traditional parallel multilevel pipelining architecture, for fixed Ethernet frames, the resolution rate can be up to 100 GB pss, but the flexibility is low. However, the kangaroo system architecture with the highest flexibility has a throughput of 40Gbpsunder the four-channel parallel parsing kernel, so it is difficult to adapt to the higher speed network. The proposed packet parser architecture can achieve the 105Gbps resolution rate at the working frequency 411MHz, which can achieve the high flexibility and throughput of the packet parser.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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