16位低功耗的Delta-Sigma调制器的设计与实现

发布时间：2018-05-30 13:30

本文选题：Delta-Sigma调制器 + 运算放大器共享技术　；参考：《哈尔滨工业大学》2017年硕士论文

【摘要】：Delta-Sigma调制器因为具有高精度、高线性度、对电路非理想特性不敏感等优点,在各类半导体传感器以及MEMS传感器中的应用越来越普遍。为了实现传感器系统的微型化与便携化,需要设计出小尺寸、低功耗的Delta-Sigma调制器。本文对可以应用于传感器接口电路的低功耗Delta-Sigma调制器进行设计实现。首先是对Delta Sigma调制器低功耗设计技术的发展进行调研,着重研究了几种常用的Delta Sigma调制器低功耗设计技术。再将多种调制器结构从功耗、信噪比、电路设计的复杂程度方面进行对比,最终决定采用使用运算放大器共享技术的单环四阶一位量化Delta Sigma调制结构进行本文的调制器设计。这种结构各级积分器输入输出摆幅较低,对电路非理想特性不敏感,适宜在低功耗设计中使用。调制器的核心模块——四级积分器,采用的是开关电容积分器,并使用运算放大器共享技术,使积分器中的运放不存在被“闲置”的情况,减少调制器中运算放大器的使用个数,达到了降低功耗的目的。调制器系统的采样频率为3.072MHz,过采样率为128,信号带宽为12kHz。采用SMIC 65nm CMOS工艺进行Delta-Sigma调制器的版图设计,遵循自上而下-自下而上的设计原则进行版图设计。版图后仿真结果表明:在输入信号幅度为0.1V,频率为3.3734kHz时,Delta-Sigma调制器的噪底在-100dB左右,SNDR为90.2dB,功耗为503.57?W,满足设计要求。
[Abstract]:Delta-Sigma modulator is widely used in semiconductor sensors and MEMS sensors because of its advantages of high precision, high linearity and insensitivity to the non-ideal characteristics of the circuit. In order to realize the miniaturization and portability of the sensor system, a small size and low power Delta-Sigma modulator should be designed. In this paper, a low power Delta-Sigma modulator which can be used in sensor interface circuit is designed and implemented. Firstly, the development of low power design technology of Delta Sigma modulator is investigated, and several commonly used low power design techniques of Delta Sigma modulator are emphatically studied. After comparing the power consumption, signal-to-noise ratio (SNR) and the complexity of circuit design, it is decided to design the modulator using the single-ring four-order one-bit quantization Delta Sigma modulation structure using operational amplifier sharing technology. Because of its low input and output swing, this kind of integrator is not sensitive to the non-ideal characteristics of the circuit and is suitable for use in low power consumption design. The core module of the modulator, the four-stage integrator, uses the switched capacitor integrator, and uses the operational amplifier sharing technology, so that there is no "idle" situation in the operational amplifier in the integrator. The power consumption is reduced by reducing the number of operational amplifiers in the modulator. The sampling frequency of the modulator is 3.072 MHz, the over-sampling rate is 128, and the signal bandwidth is 12kHz. The layout of Delta-Sigma modulator is designed by SMIC 65nm CMOS process, followed the principle of top-down and bottom-up design. The simulation results after layout show that when the input signal amplitude is 0.1V and the frequency is 3.3734kHz, the noise base of the Delta-Sigma modulator is about -100dB, the SNDR is 90.2 dB, and the power consumption is 503.57W, which meets the design requirements.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN761

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